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Same for ascii AIGERs too

This commit is contained in:
Eddie Hung 2019-02-19 15:15:50 -08:00
parent d304882cba
commit 7b026c4bc3
1 changed files with 13 additions and 6 deletions
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13
frontends/aiger/aigerparse.cc
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@ -527,13 +527,20 @@ void AigerReader::parse_aiger_ascii()
} }
else { else {
log_debug("%d is an output\n", l1); log_debug("%d is an output\n", l1);
const unsigned variable = l1 >> 1;
const bool invert = l1 & 1;
RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
wire = module->wire(wire_name);
if (!wire)
wire = createWireIfNotExists(module, l1); wire = createWireIfNotExists(module, l1);
} else {
if (wire->port_input) { if ((wire->port_input || wire->port_output)) {
RTLIL::Wire *new_wire = module->addWire(NEW_ID); RTLIL::Wire *new_wire = module->addWire(stringf("\\o%zu", outputs.size()));
module->connect(new_wire, wire); module->connect(new_wire, wire);
wire = new_wire; wire = new_wire;
} }
}
}
wire->port_output = true; wire->port_output = true;
outputs.push_back(wire); outputs.push_back(wire);
} }