mirror of https://github.com/YosysHQ/yosys.git
functional backend: rename get_input and get_current_state to input and current_state (more consistent with other methods)
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@ -499,7 +499,7 @@ public:
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vector<Node> read_results;
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factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width));
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factory.set_initial_state(mem->cell->name, MemContents(mem));
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Node node = factory.get_current_state(mem->cell->name);
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Node node = factory.current_state(mem->cell->name);
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for (size_t i = 0; i < mem->wr_ports.size(); i++) {
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const auto &wr = mem->wr_ports[i];
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if (wr.clk_enable)
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@ -543,7 +543,7 @@ public:
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log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
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"Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell));
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factory.add_state(ff.name, FunctionalIR::Sort(ff.width));
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Node q_value = factory.get_current_state(ff.name);
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Node q_value = factory.current_state(ff.name);
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factory.suggest_name(q_value, ff.name);
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factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value);
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factory.set_next_state(ff.name, enqueue(ff.sig_d));
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@ -593,7 +593,7 @@ public:
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DriveChunkWire wire_chunk = chunk.wire();
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if (wire_chunk.is_whole()) {
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if (wire_chunk.wire->port_input) {
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Node node = factory.get_input(wire_chunk.wire->name);
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Node node = factory.input(wire_chunk.wire->name);
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factory.suggest_name(node, wire_chunk.wire->name);
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factory.update_pending(pending, node);
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} else {
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@ -452,10 +452,10 @@ public:
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auto [it, inserted] = _ir._state_sorts.emplace(name, sort);
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if (!inserted) log_error("state `%s` was re-defined", name.c_str());
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}
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Node get_input(IdString name) {
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Node input(IdString name) {
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return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {});
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}
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Node get_current_state(IdString name) {
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Node current_state(IdString name) {
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return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {});
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}
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void set_output(IdString output, Node value) {
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