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functional backend: rename get_input and get_current_state to input and current_state (more consistent with other methods)

This commit is contained in:
Emily Schmidt 2024-07-25 07:59:00 +01:00
parent 95d28c22a2
commit 7ac0e92d35
2 changed files with 5 additions and 5 deletions
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6
kernel/functionalir.cc
View File

@ -499,7 +499,7 @@ public:
vector<Node> read_results; vector<Node> read_results;
factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width)); factory.add_state(mem->cell->name, FunctionalIR::Sort(ceil_log2(mem->size), mem->width));
factory.set_initial_state(mem->cell->name, MemContents(mem)); factory.set_initial_state(mem->cell->name, MemContents(mem));
Node node = factory.get_current_state(mem->cell->name); Node node = factory.current_state(mem->cell->name);
for (size_t i = 0; i < mem->wr_ports.size(); i++) { for (size_t i = 0; i < mem->wr_ports.size(); i++) {
const auto &wr = mem->wr_ports[i]; const auto &wr = mem->wr_ports[i];
if (wr.clk_enable) if (wr.clk_enable)
@ -543,7 +543,7 @@ public:
log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. " log_error("The design contains a %s flip-flop at %s. This is not supported by the functional backend. "
"Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell)); "Call async2sync or clk2fflogic to avoid this error.\n", log_id(cell->type), log_id(cell));
factory.add_state(ff.name, FunctionalIR::Sort(ff.width)); factory.add_state(ff.name, FunctionalIR::Sort(ff.width));
Node q_value = factory.get_current_state(ff.name); Node q_value = factory.current_state(ff.name);
factory.suggest_name(q_value, ff.name); factory.suggest_name(q_value, ff.name);
factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value); factory.update_pending(cell_outputs.at({cell, ID(Q)}), q_value);
factory.set_next_state(ff.name, enqueue(ff.sig_d)); factory.set_next_state(ff.name, enqueue(ff.sig_d));
@ -593,7 +593,7 @@ public:
DriveChunkWire wire_chunk = chunk.wire(); DriveChunkWire wire_chunk = chunk.wire();
if (wire_chunk.is_whole()) { if (wire_chunk.is_whole()) {
if (wire_chunk.wire->port_input) { if (wire_chunk.wire->port_input) {
Node node = factory.get_input(wire_chunk.wire->name); Node node = factory.input(wire_chunk.wire->name);
factory.suggest_name(node, wire_chunk.wire->name); factory.suggest_name(node, wire_chunk.wire->name);
factory.update_pending(pending, node); factory.update_pending(pending, node);
} else { } else {

4
kernel/functionalir.h
View File

@ -452,10 +452,10 @@ public:
auto [it, inserted] = _ir._state_sorts.emplace(name, sort); auto [it, inserted] = _ir._state_sorts.emplace(name, sort);
if (!inserted) log_error("state `%s` was re-defined", name.c_str()); if (!inserted) log_error("state `%s` was re-defined", name.c_str());
} }
Node get_input(IdString name) { Node input(IdString name) {
return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {}); return add(NodeData(Fn::input, name), Sort(_ir._input_sorts.at(name)), {});
} }
Node get_current_state(IdString name) { Node current_state(IdString name) {
return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {}); return add(NodeData(Fn::state, name), Sort(_ir._state_sorts.at(name)), {});
} }
void set_output(IdString output, Node value) { void set_output(IdString output, Node value) {