mirror of https://github.com/YosysHQ/yosys.git
opt_expr: Revisit sorting in `replace_const_cells`
Avoid building a cell-to-inbit map when sorting the cells, add a warning if we are unable to sort, and move the code treating non-combinational cells ahead of the rest (this means we don't need to pass non-combinational cells to the TopoSort object at all).
This commit is contained in:
Martin Povišer
Emil J. Tywoniak
parent
6c8ae44ae7
commit
7a8a69b65c
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@ -395,18 +395,10 @@ int get_highest_hot_index(RTLIL::SigSpec signal)
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)
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void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)
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{
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{
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CellTypes ct_combinational;
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ct_combinational.setup_internals();
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ct_combinational.setup_stdcells();
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SigMap assign_map(module);
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SigMap assign_map(module);
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dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
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dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
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TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
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for (auto cell : module->cells()) {
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dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
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dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
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for (auto cell : module->cells())
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if (design->selected(module, cell) && cell->type[0] == '$') {
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if (design->selected(module, cell) && cell->type[0] == '$') {
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if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
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if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) &&
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GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
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GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::Y)) == 1)
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@ -414,111 +406,116 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (cell->type.in(ID($mux), ID($_MUX_)) &&
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if (cell->type.in(ID($mux), ID($_MUX_)) &&
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cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
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cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
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invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::S));
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invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::S));
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if (ct_combinational.cell_known(cell->type))
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}
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for (auto &conn : cell->connections()) {
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}
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RTLIL::SigSpec sig = assign_map(conn.second);
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sig.remove_const();
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if (!noclkinv)
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if (ct_combinational.cell_input(cell->type, conn.first))
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for (auto cell : module->cells())
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cell_to_inbit[cell].insert(sig.begin(), sig.end());
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if (design->selected(module, cell)) {
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if (ct_combinational.cell_output(cell->type, conn.first))
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if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
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for (auto &bit : sig)
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handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
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outbit_to_cell[bit].insert(cell);
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}
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if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
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cells.node(cell);
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handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
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handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
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}
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}
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// Build the graph for the topological sort.
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if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
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for (auto &it_right : cell_to_inbit) {
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handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
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const int r_index = cells.node(it_right.first);
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for (auto &it_sigbit : it_right.second) {
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for (auto &it_left : outbit_to_cell[it_sigbit]) {
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const int l_index = cells.node(it_left);
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cells.edge(l_index, r_index);
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}
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}
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}
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cells.sort();
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if (cell->type.in(ID($aldff), ID($aldffe)))
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handle_polarity_inv(cell, ID::ALOAD, ID::ALOAD_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
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handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
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handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFF_N?_", "$_ALDFF_P?_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFF_?N_", "$_ALDFF_?P_", ID::L, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFFE_N??_", "$_ALDFFE_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFFE_?N?_", "$_ALDFFE_?P?_", ID::L, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFFE_??N_", "$_ALDFFE_??P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
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}
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TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
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dict<RTLIL::SigBit, Cell*> outbit_to_cell;
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for (auto cell : module->cells())
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if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_output(cell->type, conn.first))
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for (auto bit : assign_map(conn.second))
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outbit_to_cell[bit] = cell;
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cells.node(cell);
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}
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for (auto cell : module->cells())
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if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
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const int r_index = cells.node(cell);
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for (auto &conn : cell->connections())
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if (yosys_celltypes.cell_input(cell->type, conn.first))
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for (auto bit : assign_map(conn.second))
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if (outbit_to_cell.count(bit))
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cells.edge(cells.node(outbit_to_cell.at(bit)), r_index);
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}
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if (!cells.sort()) {
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// There might be a combinational loop, or there might be constants on the output of cells. Either way 'check' will find out more.
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log_warning("Unable to topologically sort combinational cells, there must be an issue with the design. Run 'check' to see what the issue is.\n");
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}
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for (auto cell : cells.sorted)
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for (auto cell : cells.sorted)
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{
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{
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#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
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#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
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#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
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#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
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if (!noclkinv)
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{
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if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memrd_v2), ID($memwr), ID($memwr_v2)))
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handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
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handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
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handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
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}
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if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
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handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($aldff), ID($aldffe)))
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handle_polarity_inv(cell, ID::ALOAD, ID::ALOAD_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
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handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
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if (cell->type.in(ID($dffe), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
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handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFF_N?_", "$_ALDFF_P?_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFF_?N_", "$_ALDFF_?P_", ID::L, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFFE_N??_", "$_ALDFFE_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFFE_?N?_", "$_ALDFFE_?P?_", ID::L, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_ALDFFE_??N_", "$_ALDFFE_??P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
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handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
|
|
||||||
|
|
||||||
handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
|
|
||||||
handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
|
|
||||||
|
|
||||||
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
|
|
||||||
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
|
|
||||||
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
|
|
||||||
}
|
|
||||||
|
|
||||||
bool detect_const_and = false;
|
bool detect_const_and = false;
|
||||||
bool detect_const_or = false;
|
bool detect_const_or = false;
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue