mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #891 from YosysHQ/xilinx_keep
xilinx: Add keep attribute where appropriate
This commit is contained in:
David Shah
GitHub
commit
7a6551de36
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@ -7,6 +7,7 @@ function xtract_cell_decl()
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{
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for dir in $libdir/xeclib $libdir/retarget; do
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[ -f $dir/$1.v ] || continue
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[ -z "$2" ] || echo $2
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egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
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sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
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s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
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@ -37,10 +38,10 @@ function xtract_cell_decl()
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xtract_cell_decl BUFMR
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xtract_cell_decl BUFMRCE
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xtract_cell_decl BUFR
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xtract_cell_decl CAPTUREE2
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xtract_cell_decl CAPTUREE2 "(* keep *)"
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# xtract_cell_decl CARRY4
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xtract_cell_decl CFGLUT5
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xtract_cell_decl DCIRESET
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xtract_cell_decl DCIRESET "(* keep *)"
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xtract_cell_decl DNA_PORT
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xtract_cell_decl DSP48E1
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xtract_cell_decl EFUSE_USR
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@ -67,10 +68,10 @@ function xtract_cell_decl()
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xtract_cell_decl IBUFDS_GTE2
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xtract_cell_decl IBUFDS_IBUFDISABLE
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xtract_cell_decl IBUFDS_INTERMDISABLE
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xtract_cell_decl ICAPE2
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xtract_cell_decl ICAPE2 "(* keep *)"
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xtract_cell_decl IDDR
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xtract_cell_decl IDDR_2CLK
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xtract_cell_decl IDELAYCTRL
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xtract_cell_decl IDELAYCTRL "(* keep *)"
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xtract_cell_decl IDELAYE2
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xtract_cell_decl IN_FIFO
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xtract_cell_decl IOBUF
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@ -112,7 +113,7 @@ function xtract_cell_decl()
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xtract_cell_decl PHY_CONTROL
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xtract_cell_decl PLLE2_ADV
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xtract_cell_decl PLLE2_BASE
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xtract_cell_decl PS7
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xtract_cell_decl PS7 "(* keep *)"
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xtract_cell_decl PULLDOWN
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xtract_cell_decl PULLUP
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xtract_cell_decl RAM128X1D
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@ -136,7 +137,7 @@ function xtract_cell_decl()
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xtract_cell_decl ROM64X1
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xtract_cell_decl SRL16E
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xtract_cell_decl SRLC32E
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xtract_cell_decl STARTUPE2
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xtract_cell_decl STARTUPE2 "(* keep *)"
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xtract_cell_decl USR_ACCESSE2
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xtract_cell_decl XADC
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} > cells_xtra.new
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@ -114,6 +114,7 @@ module BUFR (...);
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parameter SIM_DEVICE = "7SERIES";
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endmodule
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(* keep *)
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module CAPTUREE2 (...);
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parameter ONESHOT = "TRUE";
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input CAP;
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@ -130,6 +131,7 @@ module CFGLUT5 (...);
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input CDI, CE, CLK;
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endmodule
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(* keep *)
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module DCIRESET (...);
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output LOCKED;
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input RST;
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@ -2102,6 +2104,7 @@ module IBUFDS_INTERMDISABLE (...);
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input INTERMDISABLE;
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endmodule
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(* keep *)
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module ICAPE2 (...);
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parameter [31:0] DEVICE_ID = 32'h04244093;
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parameter ICAP_WIDTH = "X32";
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@ -2149,6 +2152,7 @@ module IDDR_2CLK (...);
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input S;
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endmodule
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(* keep *)
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module IDELAYCTRL (...);
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parameter SIM_DEVICE = "7SERIES";
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output RDY;
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@ -3057,6 +3061,7 @@ module PLLE2_BASE (...);
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input RST;
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endmodule
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(* keep *)
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module PS7 (...);
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output DMA0DAVALID;
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output DMA0DRREADY;
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@ -3688,6 +3693,17 @@ module PULLUP (...);
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output O;
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endmodule
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module RAM128X1D (...);
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parameter [127:0] INIT = 128'h00000000000000000000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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output DPO, SPO;
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input [6:0] A;
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input [6:0] DPRA;
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input D;
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input WCLK;
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input WE;
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endmodule
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module RAM128X1S (...);
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parameter [127:0] INIT = 128'h00000000000000000000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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@ -3695,25 +3711,6 @@ module RAM128X1S (...);
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input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
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endmodule
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module RAM128X1D (
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output DPO, SPO,
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input D, WCLK, WE,
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input [6:0] A, DPRA
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);
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parameter [127:0] INIT = 128'bx;
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parameter IS_WCLK_INVERTED = 0;
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endmodule
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module RAM64X1D (
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output DPO, SPO,
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input D, WCLK, WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter [63:0] INIT = 64'bx;
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parameter IS_WCLK_INVERTED = 0;
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endmodule
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module RAM256X1S (...);
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parameter [255:0] INIT = 256'h0;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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@ -3797,6 +3794,13 @@ module RAM64M (...);
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input WE;
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endmodule
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module RAM64X1D (...);
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parameter [63:0] INIT = 64'h0000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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output DPO, SPO;
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input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
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endmodule
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module RAM64X1S (...);
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parameter [63:0] INIT = 64'h0000000000000000;
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parameter [0:0] IS_WCLK_INVERTED = 1'b0;
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@ -3859,6 +3863,7 @@ module SRLC32E (...);
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input CE, CLK, D;
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endmodule
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(* keep *)
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module STARTUPE2 (...);
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parameter PROG_USR = "FALSE";
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parameter real SIM_CCLK_FREQ = 0.0;
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