diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index e24d24973..ce517d94b 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -5,7 +5,7 @@ module GP_DFFS(input D, CLK, nSET, output reg Q); .SRMODE(1'b1), ) _TECHMAP_REPLACE_ ( .D(D), - .CLK(C), + .CLK(CLK), .nSR(nSET), .Q(Q) ); @@ -18,7 +18,7 @@ module GP_DFFR(input D, CLK, nRST, output reg Q); .SRMODE(1'b0), ) _TECHMAP_REPLACE_ ( .D(D), - .CLK(C), + .CLK(CLK), .nSR(nRST), .Q(Q) ); diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc index b79bf7d23..879e1fe88 100644 --- a/techlibs/greenpak4/greenpak4_counters.cc +++ b/techlibs/greenpak4/greenpak4_counters.cc @@ -1,7 +1,7 @@ /* * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2016 Clifford Wolf * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index d44888998..25150ec56 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -102,6 +102,9 @@ struct SynthGreenPAK4Pass : public Pass { log(" dfflibmap -liberty +/greenpak4/gp_dff.lib\n"); log(" techmap -map +/greenpak4/cells_map.v\n"); log(" dffinit -ff GP_DFF Q INIT\n"); + log(" dffinit -ff GP_DFFR Q INIT\n"); + log(" dffinit -ff GP_DFFS Q INIT\n"); + log(" dffinit -ff GP_DFFSR Q INIT\n"); log(" clean\n"); log("\n"); log(" check:\n"); @@ -214,6 +217,9 @@ struct SynthGreenPAK4Pass : public Pass { Pass::call(design, "dfflibmap -liberty +/greenpak4/gp_dff.lib"); Pass::call(design, "techmap -map +/greenpak4/cells_map.v"); Pass::call(design, "dffinit -ff GP_DFF Q INIT"); + Pass::call(design, "dffinit -ff GP_DFFR Q INIT"); + Pass::call(design, "dffinit -ff GP_DFFS Q INIT"); + Pass::call(design, "dffinit -ff GP_DFFSR Q INIT"); Pass::call(design, "clean"); }