From 7a31fcac3b5d5df0f6fc4a53a77f95edf2cf0703 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 13 Feb 2025 16:06:51 +0100 Subject: [PATCH] CMake: Installable share files --- CMakeLists.txt | 59 +++++++++++++++++++++++++++++ backends/cxxrtl/CMakeLists.txt | 9 +++++ techlibs/achronix/CMakeLists.txt | 3 ++ techlibs/anlogic/CMakeLists.txt | 9 +++++ techlibs/common/CMakeLists.txt | 21 ++++++++++ techlibs/coolrunner2/CMakeLists.txt | 6 +++ techlibs/ecp5/CMakeLists.txt | 13 +++++++ techlibs/efinix/CMakeLists.txt | 7 ++++ techlibs/fabulous/CMakeLists.txt | 9 +++++ techlibs/gatemate/CMakeLists.txt | 13 +++++++ techlibs/gowin/CMakeLists.txt | 11 ++++++ techlibs/greenpak4/CMakeLists.txt | 9 +++++ techlibs/ice40/CMakeLists.txt | 12 ++++++ techlibs/intel/CMakeLists.txt | 12 ++++++ techlibs/intel_alm/CMakeLists.txt | 24 ++++++++++++ techlibs/lattice/CMakeLists.txt | 25 ++++++++++++ techlibs/microchip/CMakeLists.txt | 11 ++++++ techlibs/nanoxplore/CMakeLists.txt | 28 ++++++++++++++ techlibs/nexus/CMakeLists.txt | 14 +++++++ techlibs/quicklogic/CMakeLists.txt | 26 +++++++++++++ techlibs/sf2/CMakeLists.txt | 4 ++ techlibs/xilinx/CMakeLists.txt | 45 ++++++++++++++++++++++ 22 files changed, 370 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 90da4acc3..2ed16dc7d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -156,6 +156,19 @@ if (DISABLE_SPAWN) add_compile_definitions(YOSYS_DISABLE_SPAWN) endif() +function(add_share_file _dir _name) + install(FILES ${_name} DESTINATION ${_dir}) +endfunction() + +function(add_gen_share_file _dir _name) + add_share_file("${_dir}" "${_name}") +endfunction() + +function(add_include_file _dir _name) + add_share_file("share/include/${_dir}" "${_name}") +endfunction() + + add_subdirectory(kernel) add_subdirectory(libs) @@ -223,4 +236,50 @@ add_subdirectory(techlibs/quicklogic) add_subdirectory(techlibs/sf2) add_subdirectory(techlibs/xilinx) +add_include_file("kernel" "kernel/binding.h") +add_include_file("kernel" "kernel/bitpattern.h") +add_include_file("kernel" "kernel/cellaigs.h") +add_include_file("kernel" "kernel/celledges.h") +add_include_file("kernel" "kernel/celltypes.h") +add_include_file("kernel" "kernel/consteval.h") +add_include_file("kernel" "kernel/constids.inc") +add_include_file("kernel" "kernel/cost.h") +add_include_file("kernel" "kernel/drivertools.h") +add_include_file("kernel" "kernel/ff.h") +add_include_file("kernel" "kernel/ffinit.h") +add_include_file("kernel" "kernel/ffmerge.h") +add_include_file("kernel" "kernel/fmt.h") +add_include_file("kernel" "kernel/hashlib.h") +add_include_file("kernel" "kernel/json.h") +add_include_file("kernel" "kernel/log.h") +add_include_file("kernel" "kernel/macc.h") +add_include_file("kernel" "kernel/modtools.h") +add_include_file("kernel" "kernel/mem.h") +add_include_file("kernel" "kernel/qcsat.h") +add_include_file("kernel" "kernel/register.h") +add_include_file("kernel" "kernel/rtlil.h") +add_include_file("kernel" "kernel/satgen.h") +add_include_file("kernel" "kernel/scopeinfo.h") +add_include_file("kernel" "kernel/sexpr.h") +add_include_file("kernel" "kernel/sigtools.h") +add_include_file("kernel" "kernel/timinginfo.h") +add_include_file("kernel" "kernel/utils.h") +add_include_file("kernel" "kernel/yosys.h") +add_include_file("kernel" "kernel/yosys_common.h") +add_include_file("kernel" "kernel/yw.h") +add_include_file("libs/ezsat" "libs/ezsat/ezsat.h") +add_include_file("libs/ezsat" "libs/ezsat/ezminisat.h") +add_include_file("libs/sha1" "libs/sha1/sha1.h") +add_include_file("libs/json11" "libs/json11/json11.hpp") +add_include_file("passes/fsm" "passes/fsm/fsmdata.h") +add_include_file("frontends/ast" "frontends/ast/ast.h") +add_include_file("frontends/ast" "frontends/ast/ast_binding.h") +add_include_file("frontends/blif" "frontends/blif/blifparse.h") +add_include_file("backends/rtlil" "backends/rtlil/rtlil_backend.h") + +if (ENABLE_ZLIB) + add_include_file("kernel" "kernel/fstdata.h") + add_include_file("libs/fst" "libs/fst/fstapi.h") +endif() + set_property(SOURCE kernel/log.cc APPEND PROPERTY COMPILE_DEFINITIONS YOSYS_SRC="${PROJECT_SOURCE_DIR}") diff --git a/backends/cxxrtl/CMakeLists.txt b/backends/cxxrtl/CMakeLists.txt index c27c87232..1ad648170 100644 --- a/backends/cxxrtl/CMakeLists.txt +++ b/backends/cxxrtl/CMakeLists.txt @@ -5,3 +5,12 @@ target_sources(yosys_backends_cxxrtl INTERFACE ) target_link_libraries(yosys PRIVATE yosys_backends_cxxrtl) + +add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl.h") +add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl_vcd.h") +add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl_time.h") +add_include_file("backends/cxxrtl/runtime/cxxrtl" "runtime/cxxrtl/cxxrtl_replay.h") +add_include_file("backends/cxxrtl/runtime/cxxrtl/capi" "runtime/cxxrtl/capi/cxxrtl_capi.cc") +add_include_file("backends/cxxrtl/runtime/cxxrtl/capi" "runtime/cxxrtl/capi/cxxrtl_capi.h") +add_include_file("backends/cxxrtl/runtime/cxxrtl/capi" "runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc") +add_include_file("backends/cxxrtl/runtime/cxxrtl/capi" "runtime/cxxrtl/capi/cxxrtl_capi_vcd.h") diff --git a/techlibs/achronix/CMakeLists.txt b/techlibs/achronix/CMakeLists.txt index 16d125880..6229b93ba 100644 --- a/techlibs/achronix/CMakeLists.txt +++ b/techlibs/achronix/CMakeLists.txt @@ -5,3 +5,6 @@ target_sources(yosys_techlibs_achronix INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_achronix) + +add_share_file("share/achronix/speedster22i" "speedster22i/cells_sim.v") +add_share_file("share/achronix/speedster22i" "speedster22i/cells_map.v") diff --git a/techlibs/anlogic/CMakeLists.txt b/techlibs/anlogic/CMakeLists.txt index 047e76da6..7b934acc2 100644 --- a/techlibs/anlogic/CMakeLists.txt +++ b/techlibs/anlogic/CMakeLists.txt @@ -7,3 +7,12 @@ target_sources(yosys_techlibs_anlogic INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_anlogic) + +add_share_file("share/anlogic" "cells_map.v") +add_share_file("share/anlogic" "arith_map.v") +add_share_file("share/anlogic" "cells_sim.v") +add_share_file("share/anlogic" "eagle_bb.v") +add_share_file("share/anlogic" "lutrams.txt") +add_share_file("share/anlogic" "lutrams_map.v") +add_share_file("share/anlogic" "brams.txt") +add_share_file("share/anlogic" "brams_map.v") diff --git a/techlibs/common/CMakeLists.txt b/techlibs/common/CMakeLists.txt index 7ae127a94..718f20fac 100644 --- a/techlibs/common/CMakeLists.txt +++ b/techlibs/common/CMakeLists.txt @@ -28,3 +28,24 @@ target_sources(yosys_techlib_common INTERFACE add_dependencies(yosys_techlib_common yosys_techlib_common_gen) target_link_libraries(yosys PRIVATE yosys_techlib_common) + +add_share_file("share" "simlib.v") +add_share_file("share" "simcells.v") +add_share_file("share" "techmap.v") +add_share_file("share" "smtmap.v") +add_share_file("share" "pmux2mux.v") +add_share_file("share" "adff2dff.v") +add_share_file("share" "dff2ff.v") +add_share_file("share" "gate2lut.v") +add_share_file("share" "cmp2lut.v") +add_share_file("share" "cells.lib") +add_share_file("share" "mul2dsp.v") +add_share_file("share" "abc9_model.v") +add_share_file("share" "abc9_map.v") +add_share_file("share" "abc9_unmap.v") +add_share_file("share" "cmp2lcu.v") +add_share_file("share" "cmp2softlogic.v") +add_share_file("share/choices" "choices/kogge-stone.v") +add_share_file("share/choices" "choices/han-carlson.v") +add_share_file("share/choices" "choices/sklansky.v") + \ No newline at end of file diff --git a/techlibs/coolrunner2/CMakeLists.txt b/techlibs/coolrunner2/CMakeLists.txt index 9656d3b86..179416577 100644 --- a/techlibs/coolrunner2/CMakeLists.txt +++ b/techlibs/coolrunner2/CMakeLists.txt @@ -7,3 +7,9 @@ target_sources(yosys_techlibs_coolrunner2 INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_coolrunner2) + +add_share_file("share/coolrunner2" "cells_latch.v") +add_share_file("share/coolrunner2" "cells_sim.v") +add_share_file("share/coolrunner2" "cells_counter_map.v") +add_share_file("share/coolrunner2" "tff_extract.v") +add_share_file("share/coolrunner2" "xc2_dff.lib") diff --git a/techlibs/ecp5/CMakeLists.txt b/techlibs/ecp5/CMakeLists.txt index 33350aa23..e6b617be2 100644 --- a/techlibs/ecp5/CMakeLists.txt +++ b/techlibs/ecp5/CMakeLists.txt @@ -5,3 +5,16 @@ target_sources(yosys_techlibs_ecp5 INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_ecp5) + +add_share_file("share/ecp5" "cells_ff.vh") +add_share_file("share/ecp5" "cells_io.vh") +add_share_file("share/ecp5" "cells_map.v") +add_share_file("share/ecp5" "cells_sim.v") +add_share_file("share/ecp5" "cells_bb.v") +add_share_file("share/ecp5" "lutrams_map.v") +add_share_file("share/ecp5" "lutrams.txt") +add_share_file("share/ecp5" "brams_map.v") +add_share_file("share/ecp5" "brams.txt") +add_share_file("share/ecp5" "arith_map.v") +add_share_file("share/ecp5" "latches_map.v") +add_share_file("share/ecp5" "dsp_map.v") diff --git a/techlibs/efinix/CMakeLists.txt b/techlibs/efinix/CMakeLists.txt index 69f1a6cc9..e32ffe338 100644 --- a/techlibs/efinix/CMakeLists.txt +++ b/techlibs/efinix/CMakeLists.txt @@ -6,3 +6,10 @@ target_sources(yosys_techlibs_efinix INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_efinix) + +add_share_file("share/efinix" "cells_map.v") +add_share_file("share/efinix" "arith_map.v") +add_share_file("share/efinix" "cells_sim.v") +add_share_file("share/efinix" "brams_map.v") +add_share_file("share/efinix" "gbuf_map.v") +add_share_file("share/efinix" "brams.txt") diff --git a/techlibs/fabulous/CMakeLists.txt b/techlibs/fabulous/CMakeLists.txt index 3b2b4cbc0..6b2861786 100644 --- a/techlibs/fabulous/CMakeLists.txt +++ b/techlibs/fabulous/CMakeLists.txt @@ -5,3 +5,12 @@ target_sources(yosys_techlibs_fabulous INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_fabulous) + +add_share_file("share/fabulous" "cells_map.v") +add_share_file("share/fabulous" "prims.v") +add_share_file("share/fabulous" "latches_map.v") +add_share_file("share/fabulous" "ff_map.v") +add_share_file("share/fabulous" "ram_regfile.txt") +add_share_file("share/fabulous" "regfile_map.v") +add_share_file("share/fabulous" "io_map.v") +add_share_file("share/fabulous" "arith_map.v") diff --git a/techlibs/gatemate/CMakeLists.txt b/techlibs/gatemate/CMakeLists.txt index 52dc9763e..f9dcfb99a 100644 --- a/techlibs/gatemate/CMakeLists.txt +++ b/techlibs/gatemate/CMakeLists.txt @@ -6,3 +6,16 @@ target_sources(yosys_techlibs_gatemate INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_gatemate) + +add_share_file("share/gatemate" "reg_map.v") +add_share_file("share/gatemate" "mux_map.v") +add_share_file("share/gatemate" "lut_map.v") +add_share_file("share/gatemate" "mul_map.v") +add_share_file("share/gatemate" "arith_map.v") +add_share_file("share/gatemate" "cells_sim.v") +add_share_file("share/gatemate" "cells_bb.v") +add_share_file("share/gatemate" "brams_map.v") +add_share_file("share/gatemate" "brams.txt") +add_share_file("share/gatemate" "brams_init_20.vh") +add_share_file("share/gatemate" "brams_init_40.vh") +add_share_file("share/gatemate" "inv_map.v") diff --git a/techlibs/gowin/CMakeLists.txt b/techlibs/gowin/CMakeLists.txt index 74b7505e4..ecb03d6cc 100644 --- a/techlibs/gowin/CMakeLists.txt +++ b/techlibs/gowin/CMakeLists.txt @@ -5,3 +5,14 @@ target_sources(yosys_techlibs_gowin INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_gowin) + +add_share_file("share/gowin" "cells_map.v") +add_share_file("share/gowin" "cells_sim.v") +add_share_file("share/gowin" "cells_xtra_gw1n.v") +add_share_file("share/gowin" "cells_xtra_gw2a.v") +add_share_file("share/gowin" "cells_xtra_gw5a.v") +add_share_file("share/gowin" "arith_map.v") +add_share_file("share/gowin" "brams_map.v") +add_share_file("share/gowin" "brams.txt") +add_share_file("share/gowin" "lutrams_map.v") +add_share_file("share/gowin" "lutrams.txt") diff --git a/techlibs/greenpak4/CMakeLists.txt b/techlibs/greenpak4/CMakeLists.txt index 467a5fe5b..415171f4c 100644 --- a/techlibs/greenpak4/CMakeLists.txt +++ b/techlibs/greenpak4/CMakeLists.txt @@ -6,3 +6,12 @@ target_sources(yosys_techlibs_greenpak4 INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_greenpak4) + +add_share_file("share/greenpak4" "cells_blackbox.v") +add_share_file("share/greenpak4" "cells_latch.v") +add_share_file("share/greenpak4" "cells_map.v") +add_share_file("share/greenpak4" "cells_sim.v") +add_share_file("share/greenpak4" "cells_sim_ams.v") +add_share_file("share/greenpak4" "cells_sim_digital.v") +add_share_file("share/greenpak4" "cells_sim_wip.v") +add_share_file("share/greenpak4" "gp_dff.lib") diff --git a/techlibs/ice40/CMakeLists.txt b/techlibs/ice40/CMakeLists.txt index da0f12004..0e33514be 100644 --- a/techlibs/ice40/CMakeLists.txt +++ b/techlibs/ice40/CMakeLists.txt @@ -7,3 +7,15 @@ target_sources(yosys_techlibs_ice40 INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_ice40) + +add_share_file("share/ice40" "arith_map.v") +add_share_file("share/ice40" "cells_map.v") +add_share_file("share/ice40" "ff_map.v") +add_share_file("share/ice40" "cells_sim.v") +add_share_file("share/ice40" "latches_map.v") +add_share_file("share/ice40" "brams.txt") +add_share_file("share/ice40" "brams_map.v") +add_share_file("share/ice40" "spram.txt") +add_share_file("share/ice40" "spram_map.v") +add_share_file("share/ice40" "dsp_map.v") +add_share_file("share/ice40" "abc9_model.v") diff --git a/techlibs/intel/CMakeLists.txt b/techlibs/intel/CMakeLists.txt index 2d64b81fc..f79c2345e 100644 --- a/techlibs/intel/CMakeLists.txt +++ b/techlibs/intel/CMakeLists.txt @@ -5,3 +5,15 @@ target_sources(yosys_techlibs_intel INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_intel) + +add_share_file("share/intel/common" "common/m9k_bb.v") +add_share_file("share/intel/common" "common/altpll_bb.v") +add_share_file("share/intel/common" "common/brams_m9k.txt") +add_share_file("share/intel/common" "common/brams_map_m9k.v") +add_share_file("share/intel/common" "common/ff_map.v") + +# Add the cell models and mappings for the VQM backend +foreach(family IN ITEMS max10 cyclone10lp cycloneiv cycloneive) + add_share_file("share/intel/${family}" "${family}/cells_sim.v") + add_share_file("share/intel/${family}" "${family}/cells_map.v") +endforeach() diff --git a/techlibs/intel_alm/CMakeLists.txt b/techlibs/intel_alm/CMakeLists.txt index 79bd1f175..e1179f1b1 100644 --- a/techlibs/intel_alm/CMakeLists.txt +++ b/techlibs/intel_alm/CMakeLists.txt @@ -5,3 +5,27 @@ target_sources(yosys_techlibs_intel_alm INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_intel_alm) + +# Techmap +add_share_file("share/intel_alm/common" "common/abc9_map.v") +add_share_file("share/intel_alm/common" "common/abc9_unmap.v") +add_share_file("share/intel_alm/common" "common/abc9_model.v") +add_share_file("share/intel_alm/common" "common/alm_map.v") +add_share_file("share/intel_alm/common" "common/alm_sim.v") +add_share_file("share/intel_alm/common" "common/arith_alm_map.v") +add_share_file("share/intel_alm/common" "common/dff_map.v") +add_share_file("share/intel_alm/common" "common/dff_sim.v") +add_share_file("share/intel_alm/common" "common/dsp_sim.v") +add_share_file("share/intel_alm/common" "common/dsp_map.v") +add_share_file("share/intel_alm/common" "common/mem_sim.v") +add_share_file("share/intel_alm/common" "common/misc_sim.v") + +add_share_file("share/intel_alm/cyclonev" "cyclonev/cells_sim.v") + +# RAM +add_share_file("share/intel_alm/common" "common/bram_m10k.txt") +add_share_file("share/intel_alm/common" "common/bram_m10k_map.v") +add_share_file("share/intel_alm/common" "common/lutram_mlab.txt") + +# Miscellaneous +add_share_file("share/intel_alm/common" "common/megafunction_bb.v") diff --git a/techlibs/lattice/CMakeLists.txt b/techlibs/lattice/CMakeLists.txt index 08c00c74b..e9955cff6 100644 --- a/techlibs/lattice/CMakeLists.txt +++ b/techlibs/lattice/CMakeLists.txt @@ -6,3 +6,28 @@ target_sources(yosys_techlibs_lattice INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_lattice) + +add_share_file("share/lattice" "cells_ff.vh") +add_share_file("share/lattice" "cells_io.vh") +add_share_file("share/lattice" "cells_map.v") +add_share_file("share/lattice" "common_sim.vh") +add_share_file("share/lattice" "ccu2d_sim.vh") +add_share_file("share/lattice" "ccu2c_sim.vh") +add_share_file("share/lattice" "cells_sim_ecp5.v") +add_share_file("share/lattice" "cells_sim_xo2.v") +add_share_file("share/lattice" "cells_sim_xo3.v") +add_share_file("share/lattice" "cells_sim_xo3d.v") +add_share_file("share/lattice" "cells_bb_ecp5.v") +add_share_file("share/lattice" "cells_bb_xo2.v") +add_share_file("share/lattice" "cells_bb_xo3.v") +add_share_file("share/lattice" "cells_bb_xo3d.v") +add_share_file("share/lattice" "lutrams_map.v") +add_share_file("share/lattice" "lutrams.txt") +add_share_file("share/lattice" "brams_map_16kd.v") +add_share_file("share/lattice" "brams_16kd.txt") +add_share_file("share/lattice" "brams_map_8kc.v") +add_share_file("share/lattice" "brams_8kc.txt") +add_share_file("share/lattice" "arith_map_ccu2c.v") +add_share_file("share/lattice" "arith_map_ccu2d.v") +add_share_file("share/lattice" "latches_map.v") +add_share_file("share/lattice" "dsp_map_18x18.v") diff --git a/techlibs/microchip/CMakeLists.txt b/techlibs/microchip/CMakeLists.txt index c48687a4d..889858537 100644 --- a/techlibs/microchip/CMakeLists.txt +++ b/techlibs/microchip/CMakeLists.txt @@ -6,3 +6,14 @@ target_sources(yosys_techlibs_microchip INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_microchip) + +add_share_file("share/microchip" "arith_map.v") +add_share_file("share/microchip" "cells_map.v") +add_share_file("share/microchip" "cells_sim.v") +add_share_file("share/microchip" "polarfire_dsp_map.v") + +add_share_file("share/microchip" "brams_defs.vh") +add_share_file("share/microchip" "LSRAM_map.v") +add_share_file("share/microchip" "LSRAM.txt") +add_share_file("share/microchip" "uSRAM_map.v") +add_share_file("share/microchip" "uSRAM.txt") diff --git a/techlibs/nanoxplore/CMakeLists.txt b/techlibs/nanoxplore/CMakeLists.txt index bfbafed06..cfbc31982 100644 --- a/techlibs/nanoxplore/CMakeLists.txt +++ b/techlibs/nanoxplore/CMakeLists.txt @@ -6,3 +6,31 @@ target_sources(yosys_techlibs_nanoxplore INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_nanoxplore) + +# Techmap +add_share_file("share/nanoxplore" "arith_map.v") +add_share_file("share/nanoxplore" "brams_init.vh") +add_share_file("share/nanoxplore" "brams_map.v") +add_share_file("share/nanoxplore" "brams.txt") +add_share_file("share/nanoxplore" "cells_bb.v") +add_share_file("share/nanoxplore" "cells_bb_l.v") +add_share_file("share/nanoxplore" "cells_bb_m.v") +add_share_file("share/nanoxplore" "cells_bb_u.v") +add_share_file("share/nanoxplore" "cells_map.v") +add_share_file("share/nanoxplore" "cells_sim.v") +add_share_file("share/nanoxplore" "cells_sim_l.v") +add_share_file("share/nanoxplore" "cells_sim_m.v") +add_share_file("share/nanoxplore" "cells_sim_u.v") +add_share_file("share/nanoxplore" "cells_wrap.v") +add_share_file("share/nanoxplore" "cells_wrap_l.v") +add_share_file("share/nanoxplore" "cells_wrap_m.v") +add_share_file("share/nanoxplore" "cells_wrap_u.v") +add_share_file("share/nanoxplore" "io_map.v") +add_share_file("share/nanoxplore" "latches_map.v") +add_share_file("share/nanoxplore" "rf_init.vh") +add_share_file("share/nanoxplore" "rf_rams_l.txt") +add_share_file("share/nanoxplore" "rf_rams_m.txt") +add_share_file("share/nanoxplore" "rf_rams_u.txt") +add_share_file("share/nanoxplore" "rf_rams_map_l.v") +add_share_file("share/nanoxplore" "rf_rams_map_m.v") +add_share_file("share/nanoxplore" "rf_rams_map_u.v") diff --git a/techlibs/nexus/CMakeLists.txt b/techlibs/nexus/CMakeLists.txt index 7ed93a18c..a285e3407 100644 --- a/techlibs/nexus/CMakeLists.txt +++ b/techlibs/nexus/CMakeLists.txt @@ -5,3 +5,17 @@ target_sources(yosys_techlibs_nexus INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_nexus) + +add_share_file("share/nexus" "cells_map.v") +add_share_file("share/nexus" "cells_sim.v") +add_share_file("share/nexus" "parse_init.vh") +add_share_file("share/nexus" "cells_xtra.v") +add_share_file("share/nexus" "lutrams_map.v") +add_share_file("share/nexus" "lutrams.txt") +add_share_file("share/nexus" "brams_map.v") +add_share_file("share/nexus" "brams.txt") +add_share_file("share/nexus" "lrams_map.v") +add_share_file("share/nexus" "lrams.txt") +add_share_file("share/nexus" "arith_map.v") +add_share_file("share/nexus" "latches_map.v") +add_share_file("share/nexus" "dsp_map.v") diff --git a/techlibs/quicklogic/CMakeLists.txt b/techlibs/quicklogic/CMakeLists.txt index e105bf2c6..8784c85a9 100644 --- a/techlibs/quicklogic/CMakeLists.txt +++ b/techlibs/quicklogic/CMakeLists.txt @@ -23,3 +23,29 @@ target_sources(yosys_techlibs_quicklogic INTERFACE target_sources(yosys_techlibs_quicklogic PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/ql_dsp_macc_pm.h) target_link_libraries(yosys PRIVATE yosys_techlibs_quicklogic) + + +add_share_file("share/quicklogic/common" "common/cells_sim.v") +add_share_file("share/quicklogic/pp3" "pp3/ffs_map.v") +add_share_file("share/quicklogic/pp3" "pp3/lut_map.v") +add_share_file("share/quicklogic/pp3" "pp3/latches_map.v") +add_share_file("share/quicklogic/pp3" "pp3/cells_map.v") +add_share_file("share/quicklogic/pp3" "pp3/cells_sim.v") +add_share_file("share/quicklogic/pp3" "pp3/abc9_model.v") +add_share_file("share/quicklogic/pp3" "pp3/abc9_map.v") +add_share_file("share/quicklogic/pp3" "pp3/abc9_unmap.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/arith_map.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/libmap_brams.txt") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/libmap_brams_map.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/brams_map.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/brams_sim.v") +#$(eval $(call add_gen_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/cells_sim.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/ffs_map.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/dsp_sim.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/dsp_map.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/dsp_final_map.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/TDP18K_FIFO.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/ufifo_ctl.v") +add_share_file("share/quicklogic/qlf_k6n10f" "qlf_k6n10f/sram1024x18_mem.v") + diff --git a/techlibs/sf2/CMakeLists.txt b/techlibs/sf2/CMakeLists.txt index 69701df7e..76c7ae5b9 100644 --- a/techlibs/sf2/CMakeLists.txt +++ b/techlibs/sf2/CMakeLists.txt @@ -5,3 +5,7 @@ target_sources(yosys_techlibs_sf2 INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_sf2) + +add_share_file("share/sf2" "arith_map.v") +add_share_file("share/sf2" "cells_map.v") +add_share_file("share/sf2" "cells_sim.v") diff --git a/techlibs/xilinx/CMakeLists.txt b/techlibs/xilinx/CMakeLists.txt index c7e4ee59a..147303f37 100644 --- a/techlibs/xilinx/CMakeLists.txt +++ b/techlibs/xilinx/CMakeLists.txt @@ -6,3 +6,48 @@ target_sources(yosys_techlibs_xilinx INTERFACE ) target_link_libraries(yosys PRIVATE yosys_techlibs_xilinx) + +add_share_file("share/xilinx" "cells_map.v") +add_share_file("share/xilinx" "cells_sim.v") +add_share_file("share/xilinx" "cells_xtra.v") + +add_share_file("share/xilinx" "lutrams_xcv.txt") +add_share_file("share/xilinx" "lutrams_xcv_map.v") + +add_share_file("share/xilinx" "lutrams_xc5v.txt") +add_share_file("share/xilinx" "lutrams_xcu.txt") +add_share_file("share/xilinx" "lutrams_xc5v_map.v") + +add_share_file("share/xilinx" "brams_xcv.txt") +add_share_file("share/xilinx" "brams_xcv_map.v") + +add_share_file("share/xilinx" "brams_defs.vh") + +add_share_file("share/xilinx" "brams_xc2v.txt") +add_share_file("share/xilinx" "brams_xc2v_map.v") + +add_share_file("share/xilinx" "brams_xc3sda.txt") +add_share_file("share/xilinx" "brams_xc3sda_map.v") + +add_share_file("share/xilinx" "brams_xc4v.txt") +add_share_file("share/xilinx" "brams_xc4v_map.v") +add_share_file("share/xilinx" "brams_xc5v_map.v") +add_share_file("share/xilinx" "brams_xc6v_map.v") +add_share_file("share/xilinx" "brams_xcu_map.v") + +add_share_file("share/xilinx" "urams.txt") +add_share_file("share/xilinx" "urams_map.v") + +add_share_file("share/xilinx" "arith_map.v") +add_share_file("share/xilinx" "ff_map.v") +add_share_file("share/xilinx" "lut_map.v") +add_share_file("share/xilinx" "mux_map.v") +add_share_file("share/xilinx" "xc3s_mult_map.v") +add_share_file("share/xilinx" "xc3sda_dsp_map.v") +add_share_file("share/xilinx" "xc6s_dsp_map.v") +add_share_file("share/xilinx" "xc4v_dsp_map.v") +add_share_file("share/xilinx" "xc5v_dsp_map.v") +add_share_file("share/xilinx" "xc7_dsp_map.v") +add_share_file("share/xilinx" "xcu_dsp_map.v") + +add_share_file("share/xilinx" "abc9_model.v")