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gowin: Fix SDP write enable port. 

This primitive does not have a separate WRE port, so we regulate writing
using Clock Enable.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This commit is contained in:
YRabbit 2024-01-30 17:06:59 +10:00
parent 112bcb0907
commit 79c5a06673
1 changed files with 3 additions and 2 deletions
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5
techlibs/gowin/brams_map.v
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@ -324,6 +324,7 @@ input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST; wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR); wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);
wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;
generate generate
@ -347,7 +348,7 @@ if (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin
.BLKSELB(3'b000), .BLKSELB(3'b000),
.CLKA(PORT_W_CLK), .CLKA(PORT_W_CLK),
.CEA(PORT_W_CLK_EN), .CEA(WRE),
.RESETA(1'b0), .RESETA(1'b0),
.ADA(ADW), .ADA(ADW),
.DI(DI), .DI(DI),
@ -380,7 +381,7 @@ end else begin
.BLKSELB(3'b000), .BLKSELB(3'b000),
.CLKA(PORT_W_CLK), .CLKA(PORT_W_CLK),
.CEA(PORT_W_CLK_EN), .CEA(WRE),
.RESETA(1'b0), .RESETA(1'b0),
.ADA(ADW), .ADA(ADW),
.DI(DI), .DI(DI),