diff --git a/passes/pmgen/peepopt_shiftmul.pmg b/passes/pmgen/peepopt_shiftmul.pmg
index d4748ae19..d71fbf744 100644
--- a/passes/pmgen/peepopt_shiftmul.pmg
+++ b/passes/pmgen/peepopt_shiftmul.pmg
@@ -31,22 +31,18 @@ match mul
 	select mul->type.in($mul)
 	select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const()
 	index <SigSpec> port(mul, \Y) === shamt
+	filter !param(mul, \A_SIGNED).as_bool()
 endmatch
 
 code
 {
 	IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B;
-	IdString const_factor_signed = const_factor_port == \A ? \A_SIGNED : \B_SIGNED;
 	Const const_factor_cnst = port(mul, const_factor_port).as_const();
 	int const_factor = const_factor_cnst.as_int();
 
 	if (GetSize(const_factor_cnst) == 0)
 		reject;
 
-	if (const_factor_cnst.bits[GetSize(const_factor_cnst)-1] != State::S0 &&
-			param(mul, const_factor_signed).as_bool())
-		reject;
-
 	if (GetSize(const_factor_cnst) > 20)
 		reject;
 
diff --git a/tests/techmap/bug2332.ys b/tests/techmap/bug2332.ys
new file mode 100644
index 000000000..ed6b35eb2
--- /dev/null
+++ b/tests/techmap/bug2332.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [31:0] a, input signed [2:0] x, output [2:0] o);
+
+wire [5:0] t = x * 3;
+assign o = a >> t;
+
+endmodule
+EOT
+
+wreduce
+equiv_opt -assert peepopt