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Carry in/out box ordering now move to end, not swap with end

This commit is contained in:
Eddie Hung 2019-06-22 14:18:42 -07:00
parent 65c022c257
commit 7903ebe3e0
2 changed files with 46 additions and 38 deletions
backends/aiger
xaiger.cc
techlibs/xilinx
abc_xc7.box

60
backends/aiger/xaiger.cc
View File

@ -309,38 +309,46 @@ struct XAigerWriter
if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
RTLIL::Wire* last_in = nullptr, *last_out = nullptr; auto &ports = box_module->ports;
for (const auto &port_name : box_module->ports) { for (auto it = ports.begin(); it != ports.end(); ) {
RTLIL::Wire* w = box_module->wire(port_name); RTLIL::Wire* w = box_module->wire(*it);
log_assert(w); log_assert(w);
if (w->port_input) { if (w->port_input && w->attributes.count("\\abc_carry_in")) {
if (w->attributes.count("\\abc_carry_in")) { if (carry_in)
log_assert(!carry_in); log_error("More than one port with attribute 'abc_carry_in' found in module '%s'\n", log_id(box_module));
carry_in = w; carry_in = w;
} it = ports.erase(it);
log_assert(!last_in || last_in->port_id < w->port_id); continue;
last_in = w;
} }
if (w->port_output) { if (w->port_output && w->attributes.count("\\abc_carry_out")) {
if (w->attributes.count("\\abc_carry_out")) { if (carry_out)
log_assert(!carry_out); log_error("More than one port with attribute 'abc_carry_out' found in module '%s'\n", log_id(box_module));
carry_out = w; carry_out = w;
} it = ports.erase(it);
log_assert(!last_out || last_out->port_id < w->port_id); continue;
last_out = w;
} }
++it;
} }
if (carry_in) { if (!carry_in)
log_assert(last_in); log_error("Port with attribute 'abc_carry_in' not found in module '%s'\n", log_id(box_module));
std::swap(box_module->ports[carry_in->port_id-1], box_module->ports[last_in->port_id-1]); if (!carry_out)
std::swap(carry_in->port_id, last_in->port_id); log_error("Port with attribute 'abc_carry_out' not found in module '%s'\n", log_id(box_module));
}
if (carry_out) { for (const auto port_name : ports) {
log_assert(last_out); RTLIL::Wire* w = box_module->wire(port_name);
std::swap(box_module->ports[carry_out->port_id-1], box_module->ports[last_out->port_id-1]); log_assert(w);
std::swap(carry_out->port_id, last_out->port_id); if (w->port_id > carry_in->port_id)
--w->port_id;
if (w->port_id > carry_out->port_id)
--w->port_id;
log_assert(w->port_input || w->port_output);
log_assert(ports[w->port_id-1] == w->name);
} }
ports.push_back(carry_in->name);
carry_in->port_id = ports.size();
ports.push_back(carry_out->name);
carry_out->port_id = ports.size();
} }
// Fully pad all unused input connections of this box cell with S0 // Fully pad all unused input connections of this box cell with S0

24
techlibs/xilinx/abc_xc7.box
View File

@ -12,17 +12,17 @@ MUXF8 2 1 3 1
104 94 273 104 94 273
# CARRY4 + CARRY4_[ABCD]X # CARRY4 + CARRY4_[ABCD]X
# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 # Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
# (NB: carry chain input/output must be last input/output, # (NB: carry chain input/output must be last
# swapped with what normally would have been the last # input/output and have been moved there
# output, here: CI <-> S, CO <-> O # overriding the alphabetical ordering)
CARRY4 3 1 10 8 CARRY4 3 1 10 8
223 - - - 482 - - - - 222 482 - - - - 223 - - - 222
400 205 - - 598 407 - - - 334 598 407 - - - 400 205 - - 334
523 558 226 - 584 556 537 - - 239 584 556 537 - - 523 558 226 - 239
582 618 330 227 642 615 596 438 - 313 642 615 596 438 - 582 618 330 227 313
340 - - - 536 379 - - - 271 536 379 - - - 340 - - - 271
433 469 - - 494 465 445 - - 157 494 465 445 - - 433 469 - - 157
512 548 292 - 592 540 520 356 - 228 592 540 520 356 - 512 548 292 - 228
508 528 378 380 580 526 507 398 385 114 580 526 507 398 385 508 528 378 380 114