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xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v

This commit is contained in:
Eddie Hung 2020-03-04 10:32:51 -08:00
parent 968956badb
commit 78d4fff69d
2 changed files with 14 additions and 5 deletions
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11
techlibs/xilinx/abc9_map.v
View File

@ -777,6 +777,7 @@ module DSP48E1 (
wire [17:0] $B; wire [17:0] $B;
wire [47:0] $C; wire [47:0] $C;
wire [24:0] $D; wire [24:0] $D;
wire [47:0] $PCIN;
if (PREG == 0) begin if (PREG == 0) begin
if (MREG == 0 && AREG == 0) assign $A = A; if (MREG == 0 && AREG == 0) assign $A = A;
@ -788,17 +789,19 @@ module DSP48E1 (
if (CREG == 0) assign $C = C; if (CREG == 0) assign $C = C;
else assign $C = 48'bx; else assign $C = 48'bx;
assign $PCIN = PCIN;
end end
else begin else begin
assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx; assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx, $PCIN = 48'bx;
end end
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")
$__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); $__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")
$__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); $__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")
$__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); $__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else else
$error("Invalid DSP48E1 configuration"); $error("Invalid DSP48E1 configuration");
endgenerate endgenerate

8
techlibs/xilinx/abc9_model.v
View File

@ -113,10 +113,12 @@ module __NAME__ (
($A *> P) = 2823; ($A *> P) = 2823;
($B *> P) = 2690; ($B *> P) = 2690;
($C *> P) = 1325; ($C *> P) = 1325;
($PCIN *> P) = 1107;
($P *> P) = 0; ($P *> P) = 0;
($A *> PCOUT) = 2970; ($A *> PCOUT) = 2970;
($B *> PCOUT) = 2838; ($B *> PCOUT) = 2838;
($C *> PCOUT) = 1474; ($C *> PCOUT) = 1474;
($PCIN *> PCOUT) = 1255;
($PCOUT *> PCOUT) = 0; ($PCOUT *> PCOUT) = 0;
endspecify endspecify
endmodule endmodule
@ -125,12 +127,14 @@ endmodule
($A *> P) = 3806; ($A *> P) = 3806;
($B *> P) = 2690; ($B *> P) = 2690;
($C *> P) = 1325; ($C *> P) = 1325;
($D *> P) = 3700; ($D *> P) = 3717;
($PCIN *> P) = 1107;
($P *> P) = 0; ($P *> P) = 0;
($A *> PCOUT) = 3954; ($A *> PCOUT) = 3954;
($B *> PCOUT) = 2838; ($B *> PCOUT) = 2838;
($C *> PCOUT) = 1474; ($C *> PCOUT) = 1474;
($D *> PCOUT) = 3700; ($D *> PCOUT) = 3700;
($PCIN *> PCOUT) = 1255;
($PCOUT *> PCOUT) = 0; ($PCOUT *> PCOUT) = 0;
endspecify endspecify
endmodule endmodule
@ -139,10 +143,12 @@ endmodule
($A *> P) = 1523; ($A *> P) = 1523;
($B *> P) = 1509; ($B *> P) = 1509;
($C *> P) = 1325; ($C *> P) = 1325;
($PCIN *> P) = 1107;
($P *> P) = 0; ($P *> P) = 0;
($A *> PCOUT) = 1671; ($A *> PCOUT) = 1671;
($B *> PCOUT) = 1658; ($B *> PCOUT) = 1658;
($C *> PCOUT) = 1474; ($C *> PCOUT) = 1474;
($PCIN *> PCOUT) = 1255;
($PCOUT *> PCOUT) = 0; ($PCOUT *> PCOUT) = 0;
endspecify endspecify
endmodule endmodule