Docs: Assign remaining word cells to groups

Move todos to correct place.
Add todo for x-prop cells.

docs/source/cell/word_arith.rst

@@ -1,6 +1,8 @@
 Coarse arithmetics
 ------------------
 
+.. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells.
+
 Multiply-accumulate
 ~~~~~~~~~~~~~~~~~~~
 

docs/source/cell/word_binary.rst

@@ -4,6 +4,8 @@
 Binary operators
 ~~~~~~~~~~~~~~~~
 
+.. todo:: Add detail on ``$*x`` cells, `$eqx`, `$nex`, `$bweqx`, `$shiftx`
+
 All binary RTL cells have two input ports ``A`` and ``B`` and one output port
 ``Y``. They also have the following parameters:
 

docs/source/cell/word_formal.rst

@@ -12,3 +12,11 @@ Formal verification cells
    :members:
    :source:
    :linenos:
+
+Formal support cells
+~~~~~~~~~~~~~~~~~~~~
+
+.. autocellgroup:: formal_tag
+   :members:
+   :source:
+   :linenos:

docs/source/cell/word_wire.rst

@@ -0,0 +1,9 @@
+Wire cells
+-------------------------
+
+.. todo:: Add information about `$slice` and `$concat` cells.
+
+.. autocellgroup:: wire
+   :members:
+   :source:
+   :linenos:

docs/source/cell_word.rst

@@ -27,10 +27,10 @@ Simulation models for the RTL cells can be found in the file
    /cell/word_spec
    /cell/word_formal
    /cell/word_debug
+   /cell/word_wire
 
-.. todo:: Add information about `$slice` and `$concat` cells.
+.. this should raise a warning, otherwise there are word-level cells without a
-
+   'group' tag
-.. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells.
 
 .. autocellgroup:: word_other
    :caption: Other word-level cells

techlibs/common/simlib.v

@@ -585,7 +585,7 @@ endgenerate
 endmodule
 
 // --------------------------------------------------------
-
+//* group arith
 module \$fa (A, B, C, X, Y);
 
 parameter WIDTH = 1;
@@ -1477,7 +1477,7 @@ endgenerate
 endmodule
 
 // --------------------------------------------------------
-
+//* group wire
 module \$slice (A, Y);
 
 parameter OFFSET = 0;
@@ -1492,10 +1492,10 @@ assign Y = A >> OFFSET;
 endmodule
 
 // --------------------------------------------------------
-
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $concat (A, B, Y)
+//* group wire
 //-
 //- Concatenation of inputs into a single output ( Y = {B, A} ).
 //-
@@ -1870,7 +1870,7 @@ endspecify
 endmodule
 
 // --------------------------------------------------------
-
+//* group binary
 module \$bweqx (A, B, Y);
 
 parameter WIDTH = 0;
@@ -1888,7 +1888,7 @@ endgenerate
 endmodule
 
 // --------------------------------------------------------
-
+//* group mux
 module \$bwmux (A, B, S, Y);
 
 parameter WIDTH = 0;
@@ -3004,7 +3004,7 @@ endmodule
 `endif
 
 // --------------------------------------------------------
-
+//* group formal_tag
 module \$set_tag (A, SET, CLR, Y);
 
 parameter TAG = "";
@@ -3020,7 +3020,7 @@ assign Y = A;
 endmodule
 
 // --------------------------------------------------------
-
+//* group formal_tag
 module \$get_tag (A, Y);
 
 parameter TAG = "";
@@ -3034,7 +3034,7 @@ assign Y = A;
 endmodule
 
 // --------------------------------------------------------
-
+//* group formal_tag
 module \$overwrite_tag (A, SET, CLR);
 
 parameter TAG = "";
@@ -3047,7 +3047,7 @@ input [WIDTH-1:0] CLR;
 endmodule
 
 // --------------------------------------------------------
-
+//* group formal_tag
 module \$original_tag (A, Y);
 
 parameter TAG = "";
@@ -3061,7 +3061,7 @@ assign Y = A;
 endmodule
 
 // --------------------------------------------------------
-
+//* group formal_tag
 module \$future_ff (A, Y);
 
 parameter WIDTH = 0;
@@ -3074,7 +3074,7 @@ assign Y = A;
 endmodule
 
 // --------------------------------------------------------
-
+//* group debug
 (* noblackbox *)
 module \$scopeinfo ();