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Merge pull request #4210 from whitequark/fix-read_verilog-hdlname 

read_verilog: correctly format `hdlname` attribute value
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Martin Povišer 2024-02-19 16:23:06 +01:00 committed by GitHub
parent db947e4c71 b16f4900fd
commit 78b0697d33
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2 changed files with 2 additions and 2 deletions
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2
frontends/ast/ast.cc
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@ -1820,7 +1820,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
AstNode *new_ast = ast->clone();
if (!new_ast->attributes.count(ID::hdlname))
new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name));
new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name.substr(1)));
para_counter = 0;
for (auto child : new_ast->children) {

2
frontends/ast/simplify.cc
View File

@ -5662,7 +5662,7 @@ std::string AstNode::try_pop_module_prefix() const
if (current_scope.count(new_str)) {
std::string prefix = str.substr(0, pos);
auto it = current_scope_ast->attributes.find(ID::hdlname);
if ((it != current_scope_ast->attributes.end() && it->second->str == prefix)
if ((it != current_scope_ast->attributes.end() && it->second->str == prefix.substr(1))
|| prefix == current_scope_ast->str)
return new_str;
}