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Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0

This commit is contained in:
Eddie Hung 2020-01-22 14:22:03 -08:00
parent da6abc0149
commit 7858cf20a9
1 changed files with 1 additions and 1 deletions
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2
techlibs/xilinx/abc9_model.v
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@ -42,7 +42,7 @@ endmodule
// Box to emulate async behaviour of FDP* // Box to emulate async behaviour of FDP*
(* abc9_box_id = 1001, lib_whitebox *) (* abc9_box_id = 1001, lib_whitebox *)
module \$__ABC9_ASYNC1 (input A, S, output Y); module \$__ABC9_ASYNC1 (input A, S, output Y);
assign Y = S ? 1'b0 : A; assign Y = S ? 1'b1 : A;
endmodule endmodule
// Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32} // Box to emulate comb/seq behaviour of RAM{32,64} and SRL{16,32}