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fix cells_sim.v
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@ -166,15 +166,20 @@ module MCHP_SYNC_SET_DFF(
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input En,
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output Q);
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parameter [0:0] INIT = 1'b0; // unused
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reg q_ff;
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always @(posedge CLK) begin
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if (En == 1) begin
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if (Set == 0)
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Q <= 1;
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q_ff <= 1;
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else
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Q <= D;
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q_ff <= D;
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end
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end
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assign Q = q_ff;
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specify
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$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
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$setup(En, posedge CLK, 109);
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@ -192,15 +197,20 @@ module MCHP_SYNC_RESET_DFF(
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input En,
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output Q);
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parameter [0:0] INIT = 1'b0; // unused
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always @(posedge C) begin
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reg q_ff;
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always @(posedge CLK) begin
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if (En == 1) begin
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if (Reset == 0)
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Q <= 0;
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q_ff <= 0;
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else
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Q <= D;
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q_ff <= D;
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end
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end
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assign Q = q_ff;
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specify
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$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
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$setup(En, posedge CLK, 109);
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