riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fix cells_sim.v

This commit is contained in:
Chun Lin Min 2024-07-04 05:20:22 -07:00
parent e5bdc9b5c9
commit 7770fa70e1
1 changed files with 15 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
techlibs/mchp/cells_sim.v
View File

@ -166,15 +166,20 @@ module MCHP_SYNC_SET_DFF(
input En, input En,
output Q); output Q);
parameter [0:0] INIT = 1'b0; // unused parameter [0:0] INIT = 1'b0; // unused
reg q_ff;
always @(posedge CLK) begin always @(posedge CLK) begin
if (En == 1) begin if (En == 1) begin
if (Set == 0) if (Set == 0)
Q <= 1; q_ff <= 1;
else else
Q <= D; q_ff <= D;
end end
end end
assign Q = q_ff;
specify specify
$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported? $setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
$setup(En, posedge CLK, 109); $setup(En, posedge CLK, 109);
@ -192,15 +197,20 @@ module MCHP_SYNC_RESET_DFF(
input En, input En,
output Q); output Q);
parameter [0:0] INIT = 1'b0; // unused parameter [0:0] INIT = 1'b0; // unused
always @(posedge C) begin
reg q_ff;
always @(posedge CLK) begin
if (En == 1) begin if (En == 1) begin
if (Reset == 0) if (Reset == 0)
Q <= 0; q_ff <= 0;
else else
Q <= D; q_ff <= D;
end end
end end
assign Q = q_ff;
specify specify
$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported? $setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
$setup(En, posedge CLK, 109); $setup(En, posedge CLK, 109);