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Use more index patterns

This commit is contained in:
Eddie Hung 2019-09-06 12:07:35 -07:00
parent a945f6c7ef
commit 776d769941
1 changed files with 19 additions and 15 deletions
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34
passes/pmgen/xilinx_dsp.pmg
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@ -78,6 +78,7 @@ endcode
match ffAmux match ffAmux
if !sigffAmuxY.empty() if !sigffAmuxY.empty()
select ffAmux->type.in($mux) select ffAmux->type.in($mux)
index <SigSpec> port(ffAmux, \Y) === port(ffA, \D)
filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA) filter GetSize(port(ffAmux, \Y)) >= GetSize(sigA)
slice offset GetSize(port(ffAmux, \Y)) slice offset GetSize(port(ffAmux, \Y))
filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y)) filter offset+GetSize(sigA) <= GetSize(port(ffAmux, \Y))
@ -127,6 +128,7 @@ endcode
match ffBmux match ffBmux
if !sigffBmuxY.empty() if !sigffBmuxY.empty()
select ffBmux->type.in($mux) select ffBmux->type.in($mux)
index <SigSpec> port(ffBmux, \Y) === port(ffB, \D)
filter GetSize(port(ffBmux, \Y)) >= GetSize(sigB) filter GetSize(port(ffBmux, \Y)) >= GetSize(sigB)
slice offset GetSize(port(ffBmux, \Y)) slice offset GetSize(port(ffBmux, \Y))
filter offset+GetSize(sigB) <= GetSize(port(ffBmux, \Y)) filter offset+GetSize(sigB) <= GetSize(port(ffBmux, \Y))
@ -165,23 +167,32 @@ code sigM
sigM = port(ffMmux, \Y); sigM = port(ffMmux, \Y);
endcode endcode
match ffM_enable
if ffMmux
if nusers(sigM) == 2
select ffM_enable->type.in($dff)
// DSP48E1 does not support clock inversion
select param(ffM_enable, \CLK_POLARITY).as_bool()
index <SigSpec> port(ffM_enable, \D) === sigM
index <SigSpec> port(ffM_enable, \Q) === port(ffMmux, ffMenpol ? \A : \B)
endmatch
match ffM match ffM
if !ffM_enable
if param(dsp, \MREG).as_int() == 0 if param(dsp, \MREG).as_int() == 0
if nusers(sigM) == 2 if nusers(sigM) == 2
select ffM->type.in($dff) select ffM->type.in($dff)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ffM, \CLK_POLARITY).as_bool() select param(ffM, \CLK_POLARITY).as_bool()
select nusers(port(ffM, \D)) == 2 index <SigSpec> port(ffM, \D) === sigM
filter GetSize(port(ffM, \D)) <= GetSize(sigM)
filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
// Remaining bits on sigM must not have any other users
filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
// Check ffMmux (when present) is a $dff enable mux
filter !ffMmux || port(ffM, \Q) == port(ffMmux, ffMenpol ? \A : \B)
optional optional
endmatch endmatch
code clock sigM sigP code ffM clock sigM sigP
if (ffM_enable) {
log_assert(!ffM);
ffM = ffM_enable;
}
if (ffM) { if (ffM) {
sigM = port(ffM, \Q); sigM = port(ffM, \Q);
@ -194,10 +205,6 @@ code clock sigM sigP
reject; reject;
clock = c; clock = c;
} }
// Cannot have ffMmux enable mux without ffM
else if (ffMmux)
reject;
sigP = sigM; sigP = sigM;
endcode endcode
@ -311,9 +318,6 @@ code ffP sigP clock
sigP.replace(port(ffP, \D), port(ffP, \Q)); sigP.replace(port(ffP, \D), port(ffP, \Q));
} }
// Cannot have ffPmux enable mux without ffP
else if (ffPmux)
reject;
endcode endcode
match postAddMux match postAddMux