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Improve tests/ice40/macc.ys for SB_MAC16

This commit is contained in:
Eddie Hung 2019-08-30 12:22:59 -07:00
parent c1459bc748
commit 76a52712da
2 changed files with 10 additions and 7 deletions
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4
tests/ice40/macc.v
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@ -2,8 +2,8 @@
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77]. Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
*/ */
module top(clk,a,b,c,set); module top(clk,a,b,c,set);
parameter A_WIDTH = 4; parameter A_WIDTH = 6 /*4*/;
parameter B_WIDTH = 3; parameter B_WIDTH = 6 /*3*/;
input set; input set;
input clk; input clk;
input signed [(A_WIDTH - 1):0] a; input signed [(A_WIDTH - 1):0] a;

13
tests/ice40/macc.ys
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@ -1,10 +1,13 @@
read_verilog macc.v read_verilog macc.v
proc proc
hierarchy -top top hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check #equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
async2sync
equiv_opt -run prove: -assert null
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 38 t:SB_LUT4 select -assert-count 1 t:SB_MAC16
select -assert-count 3 t:SB_CARRY select -assert-none t:SB_MAC16 %% t:* %D
select -assert-count 7 t:SB_DFFSR
select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D