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Merge pull request #1833 from boqwxp/cleanup_sat_freduce 

Clean up pseudo-private member usage in `passes/sat/freduce.cc`.
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Eddie Hung 2020-03-30 11:13:06 -07:00 committed by GitHub
parent d5e2061687 9f265dfd3f
commit 769c7318e7
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1 changed files with 13 additions and 15 deletions
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28
passes/sat/freduce.cc
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@ -614,29 +614,29 @@ struct FreduceWorker
int bits_full_total = 0; int bits_full_total = 0;
std::vector<std::set<RTLIL::SigBit>> batches; std::vector<std::set<RTLIL::SigBit>> batches;
for (auto &it : module->wires_) for (auto w : module->wires())
if (it.second->port_input) { if (w->port_input) {
batches.push_back(sigmap(it.second).to_sigbit_set()); batches.push_back(sigmap(w).to_sigbit_set());
bits_full_total += it.second->width; bits_full_total += w->width;
} }
for (auto &it : module->cells_) { for (auto cell : module->cells()) {
if (ct.cell_known(it.second->type)) { if (ct.cell_known(cell->type)) {
std::set<RTLIL::SigBit> inputs, outputs; std::set<RTLIL::SigBit> inputs, outputs;
for (auto &port : it.second->connections()) { for (auto &port : cell->connections()) {
std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector(); std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
if (ct.cell_output(it.second->type, port.first)) if (ct.cell_output(cell->type, port.first))
outputs.insert(bits.begin(), bits.end()); outputs.insert(bits.begin(), bits.end());
else else
inputs.insert(bits.begin(), bits.end()); inputs.insert(bits.begin(), bits.end());
} }
std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs); std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs);
for (auto &bit : outputs) for (auto &bit : outputs)
drivers[bit] = drv; drivers[bit] = drv;
batches.push_back(outputs); batches.push_back(outputs);
bits_full_total += outputs.size(); bits_full_total += outputs.size();
} }
if (inv_mode && it.second->type == "$_NOT_") if (inv_mode && cell->type == "$_NOT_")
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y")))); inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y"))));
} }
int bits_count = 0; int bits_count = 0;
@ -828,10 +828,8 @@ struct FreducePass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
int bitcount = 0; int bitcount = 0;
for (auto &mod_it : design->modules_) { for (auto module : design->selected_modules()) {
RTLIL::Module *module = mod_it.second; bitcount += FreduceWorker(design, module).run();
if (design->selected(module))
bitcount += FreduceWorker(design, module).run();
} }
log("Rewired a total of %d signal bits.\n", bitcount); log("Rewired a total of %d signal bits.\n", bitcount);