riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

synth_xilinx -arch -> -family, consistent with older synth_intel

This commit is contained in:
Eddie Hung 2019-06-27 07:24:47 -07:00
parent ee77ee6973
commit 760819e10d
1 changed files with 8 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
techlibs/xilinx/synth_xilinx.cc
View File

@ -42,8 +42,9 @@ struct SynthXilinxPass : public ScriptPass
log(" -top <module>\n"); log(" -top <module>\n");
log(" use the specified module as top module\n"); log(" use the specified module as top module\n");
log("\n"); log("\n");
log(" -arch {xcup|xcu|xc7|xc6s}\n"); log(" -family {xcup|xcu|xc7|xc6s}\n");
log(" run synthesis for the specified Xilinx architecture\n"); log(" run synthesis for the specified Xilinx architecture\n");
log(" generate the synthesis netlist for the specified family.\n");
log(" default: xc7\n"); log(" default: xc7\n");
log("\n"); log("\n");
log(" -edif <file>\n"); log(" -edif <file>\n");
@ -90,7 +91,7 @@ struct SynthXilinxPass : public ScriptPass
log("\n"); log("\n");
} }
std::string top_opt, edif_file, blif_file, arch; std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut; bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut;
void clear_flags() YS_OVERRIDE void clear_flags() YS_OVERRIDE
@ -106,7 +107,7 @@ struct SynthXilinxPass : public ScriptPass
nosrl = false; nosrl = false;
nocarry = false; nocarry = false;
nowidelut = false; nowidelut = false;
arch = "xc7"; family = "xc7";
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -121,8 +122,8 @@ struct SynthXilinxPass : public ScriptPass
top_opt = "-top " + args[++argidx]; top_opt = "-top " + args[++argidx];
continue; continue;
} }
if (args[argidx] == "-arch" && argidx+1 < args.size()) { if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
arch = args[++argidx]; family = args[++argidx];
continue; continue;
} }
if (args[argidx] == "-edif" && argidx+1 < args.size()) { if (args[argidx] == "-edif" && argidx+1 < args.size()) {
@ -177,8 +178,8 @@ struct SynthXilinxPass : public ScriptPass
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s") if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str()); log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");