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Merge branch 'master' of github.com:YosysHQ/yosys

This commit is contained in:
Eddie Hung 2019-07-08 19:26:43 -07:00
parent 41d7d9d24b ede1ef61c5
commit 7600ffe4bd
2 changed files with 22 additions and 8 deletions
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27
passes/techmap/muxcover.cc
View File

@ -632,10 +632,15 @@ struct MuxcoverPass : public Pass {
log("Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells\n"); log("Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells\n");
log("\n"); log("\n");
log(" -mux4[=cost], -mux8[=cost], -mux16[=cost]\n"); log(" -mux4[=cost], -mux8[=cost], -mux16[=cost]\n");
log(" Use the specified types of MUXes (with optional integer costs). If none\n"); log(" Cover $_MUX_ trees using the specified types of MUXes (with optional\n");
log(" of these options are given, the effect is the same as if all of them are.\n"); log(" integer costs). If none of these options are given, the effect is the\n");
log(" Default costs: $_MUX_ = %d, $_MUX4_ = %d,\n", COST_MUX2, COST_MUX4); log(" same as if all of them are.\n");
log(" $_MUX8_ = %d, $_MUX16_ = %d\n", COST_MUX8, COST_MUX16); log(" Default costs: $_MUX4_ = %d, $_MUX8_ = %d, \n", COST_MUX4, COST_MUX8);
log(" $_MUX16_ = %d\n", COST_MUX16);
log("\n");
log(" -mux2=cost\n");
log(" Use the specified cost for $_MUX_ cells when making covering decisions.\n");
log(" Default cost: $_MUX_ = %d\n", COST_MUX2);
log("\n"); log("\n");
log(" -dmux=cost\n"); log(" -dmux=cost\n");
log(" Use the specified cost for $_MUX_ cells used in decoders.\n"); log(" Use the specified cost for $_MUX_ cells used in decoders.\n");
@ -661,6 +666,7 @@ struct MuxcoverPass : public Pass {
bool nodecode = false; bool nodecode = false;
bool nopartial = false; bool nopartial = false;
int cost_dmux = COST_DMUX; int cost_dmux = COST_DMUX;
int cost_mux2 = COST_MUX2;
int cost_mux4 = COST_MUX4; int cost_mux4 = COST_MUX4;
int cost_mux8 = COST_MUX8; int cost_mux8 = COST_MUX8;
int cost_mux16 = COST_MUX16; int cost_mux16 = COST_MUX16;
@ -669,11 +675,15 @@ struct MuxcoverPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
{ {
const auto &arg = args[argidx]; const auto &arg = args[argidx];
if (arg.size() >= 6 && arg.substr(0,6) == "-mux2=") {
cost_mux2 = std::stoi(arg.substr(6));
continue;
}
if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") { if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") {
use_mux4 = true; use_mux4 = true;
if (arg.size() > 5) { if (arg.size() > 5) {
if (arg[5] != '=') break; if (arg[5] != '=') break;
cost_mux4 = atoi(arg.substr(6).c_str()); cost_mux4 = std::stoi(arg.substr(6));
} }
continue; continue;
} }
@ -681,7 +691,7 @@ struct MuxcoverPass : public Pass {
use_mux8 = true; use_mux8 = true;
if (arg.size() > 5) { if (arg.size() > 5) {
if (arg[5] != '=') break; if (arg[5] != '=') break;
cost_mux8 = atoi(arg.substr(6).c_str()); cost_mux8 = std::stoi(arg.substr(6));
} }
continue; continue;
} }
@ -689,12 +699,12 @@ struct MuxcoverPass : public Pass {
use_mux16 = true; use_mux16 = true;
if (arg.size() > 6) { if (arg.size() > 6) {
if (arg[6] != '=') break; if (arg[6] != '=') break;
cost_mux16 = atoi(arg.substr(7).c_str()); cost_mux16 = std::stoi(arg.substr(7));
} }
continue; continue;
} }
if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") { if (arg.size() >= 6 && arg.substr(0,6) == "-dmux=") {
cost_dmux = atoi(arg.substr(6).c_str()); cost_dmux = std::stoi(arg.substr(6));
continue; continue;
} }
if (arg == "-nodecode") { if (arg == "-nodecode") {
@ -722,6 +732,7 @@ struct MuxcoverPass : public Pass {
worker.use_mux8 = use_mux8; worker.use_mux8 = use_mux8;
worker.use_mux16 = use_mux16; worker.use_mux16 = use_mux16;
worker.cost_dmux = cost_dmux; worker.cost_dmux = cost_dmux;
worker.cost_mux2 = cost_mux2;
worker.cost_mux4 = cost_mux4; worker.cost_mux4 = cost_mux4;
worker.cost_mux8 = cost_mux8; worker.cost_mux8 = cost_mux8;
worker.cost_mux16 = cost_mux16; worker.cost_mux16 = cost_mux16;

3
techlibs/intel/synth_intel.cc
View File

@ -48,6 +48,8 @@ struct SynthIntelPass : public ScriptPass {
log(" -vqm <file>\n"); log(" -vqm <file>\n");
log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
log(" output file is omitted if this parameter is not specified.\n"); log(" output file is omitted if this parameter is not specified.\n");
log(" Note that this backend has not been tested and is likely incompatible\n");
log(" with recent versions of Quartus.\n");
log("\n"); log("\n");
log(" -vpr <file>\n"); log(" -vpr <file>\n");
log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
@ -108,6 +110,7 @@ struct SynthIntelPass : public ScriptPass {
} }
if (args[argidx] == "-vqm" && argidx + 1 < args.size()) { if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
vout_file = args[++argidx]; vout_file = args[++argidx];
log_warning("The Quartus backend has not been tested recently and is likely incompatible with modern versions of Quartus.\n");
continue; continue;
} }
if (args[argidx] == "-vpr" && argidx + 1 < args.size()) { if (args[argidx] == "-vpr" && argidx + 1 < args.size()) {