mirror of https://github.com/YosysHQ/yosys.git
delete machxo2 since it is now supported in lattice
This commit is contained in:
Miodrag Milanovic
parent
e3c15f003e
commit
75fd706487
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@ -1,14 +0,0 @@
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OBJS += techlibs/machxo2/synth_machxo2.o
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$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_bb.v))
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$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams.txt))
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$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams_map.v))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams.txt))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams_map.v))
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$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/arith_map.v))
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@ -1,90 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Copyright (C) 2018 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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(* techmap_celltype = "$alu" *)
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module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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function integer round_up2;
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input integer N;
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begin
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round_up2 = ((N + 1) / 2) * 2;
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end
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endfunction
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localparam Y_WIDTH2 = round_up2(Y_WIDTH);
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(* force_downto *)
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wire [Y_WIDTH2-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] BX = B_buf;
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(* force_downto *)
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wire [Y_WIDTH2-1:0] C = {CO, CI};
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(* force_downto *)
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wire [Y_WIDTH2-1:0] FCO, Y1;
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genvar i;
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generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
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CCU2D #(
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.INIT0(16'b0101_1010_1001_0110),
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.INIT1(16'b0101_1010_1001_0110),
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.INJECT1_0("NO"),
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.INJECT1_1("NO")
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) ccu2d_i (
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.CIN(C[i]),
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.A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b0),
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.A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b0),
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.S0(Y[i]), .S1(Y1[i]),
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.COUT(FCO[i])
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);
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assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
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if (i+1 < Y_WIDTH) begin
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assign CO[i+1] = FCO[i];
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assign Y[i+1] = Y1[i];
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end
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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@ -1,50 +0,0 @@
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ram block $__DP8KC_ {
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abits 13;
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widths 1 2 4 9 per_port;
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cost 64;
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init no_undef;
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port srsw "A" "B" {
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clock posedge;
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clken;
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portoption "WRITEMODE" "NORMAL" {
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rdwr no_change;
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}
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portoption "WRITEMODE" "WRITETHROUGH" {
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rdwr new;
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}
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portoption "WRITEMODE" "READBEFOREWRITE" {
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rdwr old;
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}
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated block_wr;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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}
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ram block $__PDPW8KC_ {
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abits 13;
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widths 1 2 4 9 18 per_port;
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byte 9;
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cost 64;
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init no_undef;
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port sr "R" {
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clock posedge;
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clken;
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option "RESETMODE" "SYNC" {
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rdsrst zero ungated;
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}
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option "RESETMODE" "ASYNC" {
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rdarst zero;
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}
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rdinit zero;
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}
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port sw "W" {
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width 18;
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clock posedge;
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clken;
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}
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}
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@ -1,337 +0,0 @@
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module $__DP8KC_ (...);
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parameter INIT = 0;
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parameter OPTION_RESETMODE = "SYNC";
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parameter PORT_A_WIDTH = 18;
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parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [12:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_WIDTH = 18;
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parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input [12:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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function [319:0] init_slice;
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input integer idx;
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integer i, j;
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init_slice = 0;
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for (i = 0; i < 16; i = i + 1) begin
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init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
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end
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endfunction
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wire [8:0] DOA;
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wire [8:0] DOB;
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wire [8:0] DIA = PORT_A_WR_DATA;
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wire [8:0] DIB = PORT_B_WR_DATA;
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assign PORT_A_RD_DATA = DOA;
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assign PORT_B_RD_DATA = DOB;
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DP8KC #(
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.INITVAL_00(init_slice('h00)),
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.INITVAL_01(init_slice('h01)),
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.INITVAL_02(init_slice('h02)),
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.INITVAL_03(init_slice('h03)),
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.INITVAL_04(init_slice('h04)),
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.INITVAL_05(init_slice('h05)),
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.INITVAL_06(init_slice('h06)),
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.INITVAL_07(init_slice('h07)),
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.INITVAL_08(init_slice('h08)),
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.INITVAL_09(init_slice('h09)),
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.INITVAL_0A(init_slice('h0a)),
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.INITVAL_0B(init_slice('h0b)),
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.INITVAL_0C(init_slice('h0c)),
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.INITVAL_0D(init_slice('h0d)),
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.INITVAL_0E(init_slice('h0e)),
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.INITVAL_0F(init_slice('h0f)),
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.INITVAL_10(init_slice('h10)),
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.INITVAL_11(init_slice('h11)),
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.INITVAL_12(init_slice('h12)),
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.INITVAL_13(init_slice('h13)),
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.INITVAL_14(init_slice('h14)),
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.INITVAL_15(init_slice('h15)),
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.INITVAL_16(init_slice('h16)),
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.INITVAL_17(init_slice('h17)),
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.INITVAL_18(init_slice('h18)),
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.INITVAL_19(init_slice('h19)),
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.INITVAL_1A(init_slice('h1a)),
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.INITVAL_1B(init_slice('h1b)),
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.INITVAL_1C(init_slice('h1c)),
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.INITVAL_1D(init_slice('h1d)),
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.INITVAL_1E(init_slice('h1e)),
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.INITVAL_1F(init_slice('h1f)),
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.DATA_WIDTH_A(PORT_A_WIDTH),
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.DATA_WIDTH_B(PORT_B_WIDTH),
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.REGMODE_A("NOREG"),
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.REGMODE_B("NOREG"),
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.RESETMODE(OPTION_RESETMODE),
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.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
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.CSDECODE_A("0b000"),
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.CSDECODE_B("0b000"),
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.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
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.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
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.GSR("AUTO")
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) _TECHMAP_REPLACE_ (
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.CLKA(PORT_A_CLK),
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.WEA(PORT_A_WR_EN),
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.CEA(PORT_A_CLK_EN),
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.OCEA(1'b1),
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.RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
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.CSA0(1'b0),
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.CSA1(1'b0),
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.CSA2(1'b0),
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.ADA0(PORT_A_WIDTH == 9 ? 1'b1 : PORT_A_ADDR[0]),
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.ADA1(PORT_A_ADDR[1]),
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.ADA2(PORT_A_ADDR[2]),
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.ADA3(PORT_A_ADDR[3]),
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.ADA4(PORT_A_ADDR[4]),
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.ADA5(PORT_A_ADDR[5]),
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.ADA6(PORT_A_ADDR[6]),
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.ADA7(PORT_A_ADDR[7]),
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.ADA8(PORT_A_ADDR[8]),
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.ADA9(PORT_A_ADDR[9]),
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.ADA10(PORT_A_ADDR[10]),
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.ADA11(PORT_A_ADDR[11]),
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.ADA12(PORT_A_ADDR[12]),
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.DIA0(DIA[0]),
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.DIA1(DIA[1]),
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.DIA2(DIA[2]),
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.DIA3(DIA[3]),
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.DIA4(DIA[4]),
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.DIA5(DIA[5]),
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.DIA6(DIA[6]),
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.DIA7(DIA[7]),
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.DIA8(DIA[8]),
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.DOA0(DOA[0]),
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.DOA1(DOA[1]),
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.DOA2(DOA[2]),
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.DOA3(DOA[3]),
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.DOA4(DOA[4]),
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.DOA5(DOA[5]),
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.DOA6(DOA[6]),
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.DOA7(DOA[7]),
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.DOA8(DOA[8]),
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.CLKB(PORT_B_CLK),
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.WEB(PORT_B_WR_EN),
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.CEB(PORT_B_CLK_EN),
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.OCEB(1'b1),
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.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
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.CSB0(1'b0),
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.CSB1(1'b0),
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.CSB2(1'b0),
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.ADB0(PORT_B_WIDTH == 9 ? 1'b1 : PORT_B_ADDR[0]),
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.ADB1(PORT_B_ADDR[1]),
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.ADB2(PORT_B_ADDR[2]),
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||||||
.ADB3(PORT_B_ADDR[3]),
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||||||
.ADB4(PORT_B_ADDR[4]),
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||||||
.ADB5(PORT_B_ADDR[5]),
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||||||
.ADB6(PORT_B_ADDR[6]),
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||||||
.ADB7(PORT_B_ADDR[7]),
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.ADB8(PORT_B_ADDR[8]),
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.ADB9(PORT_B_ADDR[9]),
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.ADB10(PORT_B_ADDR[10]),
|
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||||||
.ADB11(PORT_B_ADDR[11]),
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.ADB12(PORT_B_ADDR[12]),
|
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.DIB0(DIB[0]),
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||||||
.DIB1(DIB[1]),
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.DIB2(DIB[2]),
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|
||||||
.DIB3(DIB[3]),
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.DIB4(DIB[4]),
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||||||
.DIB5(DIB[5]),
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.DIB6(DIB[6]),
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|
||||||
.DIB7(DIB[7]),
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|
||||||
.DIB8(DIB[8]),
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|
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.DOB0(DOB[0]),
|
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.DOB1(DOB[1]),
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.DOB2(DOB[2]),
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||||||
.DOB3(DOB[3]),
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|
||||||
.DOB4(DOB[4]),
|
|
||||||
.DOB5(DOB[5]),
|
|
||||||
.DOB6(DOB[6]),
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|
||||||
.DOB7(DOB[7]),
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.DOB8(DOB[8]),
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|
||||||
);
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|
||||||
|
|
||||||
endmodule
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|
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|
|
||||||
|
|
||||||
module $__PDPW8KC_ (...);
|
|
||||||
|
|
||||||
parameter INIT = 0;
|
|
||||||
parameter OPTION_RESETMODE = "SYNC";
|
|
||||||
|
|
||||||
parameter PORT_R_WIDTH = 18;
|
|
||||||
|
|
||||||
input PORT_R_CLK;
|
|
||||||
input PORT_R_CLK_EN;
|
|
||||||
input PORT_R_RD_SRST;
|
|
||||||
input PORT_R_RD_ARST;
|
|
||||||
input [12:0] PORT_R_ADDR;
|
|
||||||
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
|
|
||||||
|
|
||||||
parameter PORT_W_WIDTH = 18;
|
|
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parameter PORT_W_WR_EN_WIDTH = 2;
|
|
||||||
|
|
||||||
input PORT_W_CLK;
|
|
||||||
input PORT_W_CLK_EN;
|
|
||||||
input [12:0] PORT_W_ADDR;
|
|
||||||
input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
|
|
||||||
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
|
|
||||||
|
|
||||||
function [319:0] init_slice;
|
|
||||||
input integer idx;
|
|
||||||
integer i, j;
|
|
||||||
init_slice = 0;
|
|
||||||
for (i = 0; i < 16; i = i + 1) begin
|
|
||||||
init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
wire [17:0] DI = PORT_W_WR_DATA;
|
|
||||||
wire [17:0] DO;
|
|
||||||
|
|
||||||
assign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9];
|
|
||||||
|
|
||||||
DP8KC #(
|
|
||||||
.INITVAL_00(init_slice('h00)),
|
|
||||||
.INITVAL_01(init_slice('h01)),
|
|
||||||
.INITVAL_02(init_slice('h02)),
|
|
||||||
.INITVAL_03(init_slice('h03)),
|
|
||||||
.INITVAL_04(init_slice('h04)),
|
|
||||||
.INITVAL_05(init_slice('h05)),
|
|
||||||
.INITVAL_06(init_slice('h06)),
|
|
||||||
.INITVAL_07(init_slice('h07)),
|
|
||||||
.INITVAL_08(init_slice('h08)),
|
|
||||||
.INITVAL_09(init_slice('h09)),
|
|
||||||
.INITVAL_0A(init_slice('h0a)),
|
|
||||||
.INITVAL_0B(init_slice('h0b)),
|
|
||||||
.INITVAL_0C(init_slice('h0c)),
|
|
||||||
.INITVAL_0D(init_slice('h0d)),
|
|
||||||
.INITVAL_0E(init_slice('h0e)),
|
|
||||||
.INITVAL_0F(init_slice('h0f)),
|
|
||||||
.INITVAL_10(init_slice('h10)),
|
|
||||||
.INITVAL_11(init_slice('h11)),
|
|
||||||
.INITVAL_12(init_slice('h12)),
|
|
||||||
.INITVAL_13(init_slice('h13)),
|
|
||||||
.INITVAL_14(init_slice('h14)),
|
|
||||||
.INITVAL_15(init_slice('h15)),
|
|
||||||
.INITVAL_16(init_slice('h16)),
|
|
||||||
.INITVAL_17(init_slice('h17)),
|
|
||||||
.INITVAL_18(init_slice('h18)),
|
|
||||||
.INITVAL_19(init_slice('h19)),
|
|
||||||
.INITVAL_1A(init_slice('h1a)),
|
|
||||||
.INITVAL_1B(init_slice('h1b)),
|
|
||||||
.INITVAL_1C(init_slice('h1c)),
|
|
||||||
.INITVAL_1D(init_slice('h1d)),
|
|
||||||
.INITVAL_1E(init_slice('h1e)),
|
|
||||||
.INITVAL_1F(init_slice('h1f)),
|
|
||||||
.DATA_WIDTH_A(PORT_W_WIDTH),
|
|
||||||
.DATA_WIDTH_B(PORT_R_WIDTH),
|
|
||||||
.REGMODE_A("NOREG"),
|
|
||||||
.REGMODE_B("NOREG"),
|
|
||||||
.RESETMODE(OPTION_RESETMODE),
|
|
||||||
.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
|
|
||||||
.CSDECODE_A("0b000"),
|
|
||||||
.CSDECODE_B("0b000"),
|
|
||||||
.GSR("AUTO")
|
|
||||||
) _TECHMAP_REPLACE_ (
|
|
||||||
.CLKA(PORT_W_CLK),
|
|
||||||
.WEA(PORT_W_WIDTH >= 9 ? 1'b1 : PORT_W_WR_EN[0]),
|
|
||||||
.CEA(PORT_W_CLK_EN),
|
|
||||||
.OCEA(1'b0),
|
|
||||||
.RSTA(1'b0),
|
|
||||||
.CSA0(1'b0),
|
|
||||||
.CSA1(1'b0),
|
|
||||||
.CSA2(1'b0),
|
|
||||||
.ADA0(PORT_W_WIDTH >= 9 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),
|
|
||||||
.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),
|
|
||||||
.ADA2(PORT_W_ADDR[2]),
|
|
||||||
.ADA3(PORT_W_ADDR[3]),
|
|
||||||
.ADA4(PORT_W_ADDR[4]),
|
|
||||||
.ADA5(PORT_W_ADDR[5]),
|
|
||||||
.ADA6(PORT_W_ADDR[6]),
|
|
||||||
.ADA7(PORT_W_ADDR[7]),
|
|
||||||
.ADA8(PORT_W_ADDR[8]),
|
|
||||||
.ADA9(PORT_W_ADDR[9]),
|
|
||||||
.ADA10(PORT_W_ADDR[10]),
|
|
||||||
.ADA11(PORT_W_ADDR[11]),
|
|
||||||
.ADA12(PORT_W_ADDR[12]),
|
|
||||||
.DIA0(DI[0]),
|
|
||||||
.DIA1(DI[1]),
|
|
||||||
.DIA2(DI[2]),
|
|
||||||
.DIA3(DI[3]),
|
|
||||||
.DIA4(DI[4]),
|
|
||||||
.DIA5(DI[5]),
|
|
||||||
.DIA6(DI[6]),
|
|
||||||
.DIA7(DI[7]),
|
|
||||||
.DIA8(DI[8]),
|
|
||||||
.DIB0(DI[9]),
|
|
||||||
.DIB1(DI[10]),
|
|
||||||
.DIB2(DI[11]),
|
|
||||||
.DIB3(DI[12]),
|
|
||||||
.DIB4(DI[13]),
|
|
||||||
.DIB5(DI[14]),
|
|
||||||
.DIB6(DI[15]),
|
|
||||||
.DIB7(DI[16]),
|
|
||||||
.DIB8(DI[17]),
|
|
||||||
|
|
||||||
.CLKB(PORT_R_CLK),
|
|
||||||
.WEB(1'b0),
|
|
||||||
.CEB(PORT_R_CLK_EN),
|
|
||||||
.OCEB(1'b1),
|
|
||||||
.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
|
|
||||||
.CSB0(1'b0),
|
|
||||||
.CSB1(1'b0),
|
|
||||||
.CSB2(1'b0),
|
|
||||||
.ADB0(PORT_R_ADDR[0]),
|
|
||||||
.ADB1(PORT_R_ADDR[1]),
|
|
||||||
.ADB2(PORT_R_ADDR[2]),
|
|
||||||
.ADB3(PORT_R_ADDR[3]),
|
|
||||||
.ADB4(PORT_R_ADDR[4]),
|
|
||||||
.ADB5(PORT_R_ADDR[5]),
|
|
||||||
.ADB6(PORT_R_ADDR[6]),
|
|
||||||
.ADB7(PORT_R_ADDR[7]),
|
|
||||||
.ADB8(PORT_R_ADDR[8]),
|
|
||||||
.ADB9(PORT_R_ADDR[9]),
|
|
||||||
.ADB10(PORT_R_ADDR[10]),
|
|
||||||
.ADB11(PORT_R_ADDR[11]),
|
|
||||||
.ADB12(PORT_R_ADDR[12]),
|
|
||||||
.DOA0(DO[0]),
|
|
||||||
.DOA1(DO[1]),
|
|
||||||
.DOA2(DO[2]),
|
|
||||||
.DOA3(DO[3]),
|
|
||||||
.DOA4(DO[4]),
|
|
||||||
.DOA5(DO[5]),
|
|
||||||
.DOA6(DO[6]),
|
|
||||||
.DOA7(DO[7]),
|
|
||||||
.DOA8(DO[8]),
|
|
||||||
.DOB0(DO[9]),
|
|
||||||
.DOB1(DO[10]),
|
|
||||||
.DOB2(DO[11]),
|
|
||||||
.DOB3(DO[12]),
|
|
||||||
.DOB4(DO[13]),
|
|
||||||
.DOB5(DO[14]),
|
|
||||||
.DOB6(DO[15]),
|
|
||||||
.DOB7(DO[16]),
|
|
||||||
.DOB8(DO[17]),
|
|
||||||
);
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
@ -1,227 +0,0 @@
|
||||||
(* blackbox *)
|
|
||||||
module EHXPLLJ (
|
|
||||||
input CLKI, CLKFB,
|
|
||||||
input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP,
|
|
||||||
input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD,
|
|
||||||
input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE,
|
|
||||||
input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0,
|
|
||||||
input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0,
|
|
||||||
output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK,
|
|
||||||
output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK,
|
|
||||||
output DPHSRC, CLKINTFB
|
|
||||||
);
|
|
||||||
parameter CLKI_DIV = 1;
|
|
||||||
parameter CLKFB_DIV = 1;
|
|
||||||
parameter CLKOP_DIV = 8;
|
|
||||||
parameter CLKOS_DIV = 8;
|
|
||||||
parameter CLKOS2_DIV = 8;
|
|
||||||
parameter CLKOS3_DIV = 8;
|
|
||||||
parameter CLKOP_ENABLE = "ENABLED";
|
|
||||||
parameter CLKOS_ENABLE = "ENABLED";
|
|
||||||
parameter CLKOS2_ENABLE = "ENABLED";
|
|
||||||
parameter CLKOS3_ENABLE = "ENABLED";
|
|
||||||
parameter VCO_BYPASS_A0 = "DISABLED";
|
|
||||||
parameter VCO_BYPASS_B0 = "DISABLED";
|
|
||||||
parameter VCO_BYPASS_C0 = "DISABLED";
|
|
||||||
parameter VCO_BYPASS_D0 = "DISABLED";
|
|
||||||
parameter CLKOP_CPHASE = 0;
|
|
||||||
parameter CLKOS_CPHASE = 0;
|
|
||||||
parameter CLKOS2_CPHASE = 0;
|
|
||||||
parameter CLKOS3_CPHASE = 0;
|
|
||||||
parameter CLKOP_FPHASE = 0;
|
|
||||||
parameter CLKOS_FPHASE = 0;
|
|
||||||
parameter CLKOS2_FPHASE = 0;
|
|
||||||
parameter CLKOS3_FPHASE = 0;
|
|
||||||
parameter FEEDBK_PATH = "CLKOP";
|
|
||||||
parameter FRACN_ENABLE = "DISABLED";
|
|
||||||
parameter FRACN_DIV = 0;
|
|
||||||
parameter CLKOP_TRIM_POL = "RISING";
|
|
||||||
parameter CLKOP_TRIM_DELAY = 0;
|
|
||||||
parameter CLKOS_TRIM_POL = "RISING";
|
|
||||||
parameter CLKOS_TRIM_DELAY = 0;
|
|
||||||
parameter PLL_USE_WB = "DISABLED";
|
|
||||||
parameter PREDIVIDER_MUXA1 = 0;
|
|
||||||
parameter PREDIVIDER_MUXB1 = 0;
|
|
||||||
parameter PREDIVIDER_MUXC1 = 0;
|
|
||||||
parameter PREDIVIDER_MUXD1 = 0;
|
|
||||||
parameter OUTDIVIDER_MUXA2 = "DIVA";
|
|
||||||
parameter OUTDIVIDER_MUXB2 = "DIVB";
|
|
||||||
parameter OUTDIVIDER_MUXC2 = "DIVC";
|
|
||||||
parameter OUTDIVIDER_MUXD2 = "DIVD";
|
|
||||||
parameter PLL_LOCK_MODE = 0;
|
|
||||||
parameter STDBY_ENABLE = "DISABLED";
|
|
||||||
parameter DPHASE_SOURCE = "DISABLED";
|
|
||||||
parameter PLLRST_ENA = "DISABLED";
|
|
||||||
parameter MRST_ENA = "DISABLED";
|
|
||||||
parameter DCRST_ENA = "DISABLED";
|
|
||||||
parameter DDRST_ENA = "DISABLED";
|
|
||||||
parameter INTFB_WAKE = "DISABLED";
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* blackbox *)
|
|
||||||
module OSCH #(
|
|
||||||
parameter NOM_FREQ = "2.08"
|
|
||||||
) (
|
|
||||||
input STDBY,
|
|
||||||
output OSC,
|
|
||||||
output SEDSTDBY
|
|
||||||
);
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* blackbox *)
|
|
||||||
module DCCA (
|
|
||||||
input CLKI,
|
|
||||||
input CE,
|
|
||||||
output CLKO
|
|
||||||
);
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* blackbox *)
|
|
||||||
module DCMA (
|
|
||||||
input CLK0,
|
|
||||||
input CLK1,
|
|
||||||
input SEL,
|
|
||||||
output DCMOUT
|
|
||||||
);
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* blackbox *)
|
|
||||||
module PDPW8KC (
|
|
||||||
input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
|
|
||||||
input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0,
|
|
||||||
input BE1, BE0,
|
|
||||||
input CEW, CLKW, CSW2, CSW1, CSW0,
|
|
||||||
input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0,
|
|
||||||
input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST,
|
|
||||||
output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
|
|
||||||
);
|
|
||||||
parameter DATA_WIDTH_W = 18;
|
|
||||||
parameter DATA_WIDTH_R = 9;
|
|
||||||
|
|
||||||
parameter GSR = "ENABLED";
|
|
||||||
|
|
||||||
parameter REGMODE = "NOREG";
|
|
||||||
|
|
||||||
parameter RESETMODE = "SYNC";
|
|
||||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
|
||||||
|
|
||||||
parameter CSDECODE_W = "0b000";
|
|
||||||
parameter CSDECODE_R = "0b000";
|
|
||||||
|
|
||||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INIT_DATA = "STATIC";
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* blackbox *)
|
|
||||||
module SP8KC (
|
|
||||||
input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0,
|
|
||||||
input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0,
|
|
||||||
input CE, OCE, CLK, WE, CS2, CS1, CS0, RST,
|
|
||||||
output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0
|
|
||||||
);
|
|
||||||
parameter DATA_WIDTH = 9;
|
|
||||||
parameter GSR = "ENABLED";
|
|
||||||
|
|
||||||
parameter REGMODE = "NOREG";
|
|
||||||
|
|
||||||
parameter RESETMODE = "SYNC";
|
|
||||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
|
||||||
|
|
||||||
parameter CSDECODE = "0b000";
|
|
||||||
|
|
||||||
parameter WRITEMODE = "NORMAL";
|
|
||||||
|
|
||||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INIT_DATA = "STATIC";
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* blackbox *)
|
|
||||||
module FIFO8KB (
|
|
||||||
input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17,
|
|
||||||
input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI,
|
|
||||||
output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17,
|
|
||||||
input EF, AEF, AFF, FF
|
|
||||||
);
|
|
||||||
parameter DATA_WIDTH_W = 18;
|
|
||||||
parameter DATA_WIDTH_R = 18;
|
|
||||||
|
|
||||||
parameter GSR = "DISABLED";
|
|
||||||
|
|
||||||
parameter REGMODE = "NOREG";
|
|
||||||
|
|
||||||
parameter RESETMODE = "ASYNC";
|
|
||||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
|
||||||
|
|
||||||
parameter CSDECODE_W = "0b00";
|
|
||||||
parameter CSDECODE_R = "0b00";
|
|
||||||
|
|
||||||
parameter AEPOINTER = "0b00000000000000";
|
|
||||||
parameter AEPOINTER1 = "0b00000000000000";
|
|
||||||
parameter AFPOINTER = "0b00000000000000";
|
|
||||||
parameter AFPOINTER1 = "0b00000000000000";
|
|
||||||
parameter FULLPOINTER = "0b00000000000000";
|
|
||||||
parameter FULLPOINTER1 = "0b00000000000000";
|
|
||||||
endmodule
|
|
||||||
|
|
@ -1,117 +0,0 @@
|
||||||
module \$_DFF_N_ (input D, C, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
else
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFF_P_ (input D, C, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
else
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_NN_ (input D, C, E, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
else
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_PN_ (input D, C, E, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
else
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_NP_ (input D, C, E, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
else
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_PP_ (input D, C, E, output Q);
|
|
||||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
|
||||||
generate if (_TECHMAP_WIREINIT_Q_ === 1'b1)
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
else
|
|
||||||
TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q));
|
|
||||||
endgenerate
|
|
||||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
|
|
||||||
module \$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
|
|
||||||
module \$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
|
|
||||||
module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
|
|
||||||
module \$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule
|
|
||||||
|
|
||||||
module \$lut (A, Y);
|
|
||||||
parameter WIDTH = 0;
|
|
||||||
parameter LUT = 0;
|
|
||||||
input [WIDTH-1:0] A;
|
|
||||||
output Y;
|
|
||||||
|
|
||||||
localparam rep = 1<<(4-WIDTH);
|
|
||||||
wire [3:0] I;
|
|
||||||
|
|
||||||
generate
|
|
||||||
if(WIDTH == 1) begin
|
|
||||||
assign I = {1'b0, 1'b0, 1'b0, A[0]};
|
|
||||||
end else if(WIDTH == 2) begin
|
|
||||||
assign I = {1'b0, 1'b0, A[1], A[0]};
|
|
||||||
end else if(WIDTH == 3) begin
|
|
||||||
assign I = {1'b0, A[2], A[1], A[0]};
|
|
||||||
end else if(WIDTH == 4) begin
|
|
||||||
assign I = {A[3], A[2], A[1], A[0]};
|
|
||||||
end else begin
|
|
||||||
wire _TECHMAP_FAIL_ = 1;
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y));
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
`include "cells_io.vh"
|
|
||||||
|
|
@ -1,385 +0,0 @@
|
||||||
module LUT2(input A, B, output Z);
|
|
||||||
parameter [3:0] INIT = 4'h0;
|
|
||||||
wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
|
|
||||||
assign Z = A ? s1[1] : s1[0];
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module LUT4 #(
|
|
||||||
parameter [15:0] INIT = 0
|
|
||||||
) (
|
|
||||||
input A, B, C, D,
|
|
||||||
output Z
|
|
||||||
);
|
|
||||||
// This form of LUT propagates as few x's as possible.
|
|
||||||
wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
|
|
||||||
wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
|
|
||||||
wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
|
|
||||||
assign Z = A ? s1[1] : s1[0];
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module TRELLIS_FF #(
|
|
||||||
parameter GSR = "ENABLED",
|
|
||||||
parameter CEMUX = "1",
|
|
||||||
parameter CLKMUX = "0",
|
|
||||||
parameter LSRMUX = "LSR",
|
|
||||||
parameter LSRONMUX = "LSRMUX",
|
|
||||||
parameter SRMODE = "LSR_OVER_CE",
|
|
||||||
parameter REGSET = "SET",
|
|
||||||
parameter REGMODE = "FF"
|
|
||||||
) (
|
|
||||||
input CLK, DI, LSR, CE,
|
|
||||||
output reg Q
|
|
||||||
);
|
|
||||||
|
|
||||||
wire muxce;
|
|
||||||
generate
|
|
||||||
case (CEMUX)
|
|
||||||
"1": assign muxce = 1'b1;
|
|
||||||
"0": assign muxce = 1'b0;
|
|
||||||
"INV": assign muxce = ~CE;
|
|
||||||
default: assign muxce = CE;
|
|
||||||
endcase
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
|
|
||||||
wire muxlsron = (LSRONMUX == "LSRMUX") ? muxlsr : 1'b0;
|
|
||||||
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
|
|
||||||
wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
|
|
||||||
|
|
||||||
initial Q = srval;
|
|
||||||
|
|
||||||
generate
|
|
||||||
if (REGMODE == "FF") begin
|
|
||||||
if (SRMODE == "ASYNC") begin
|
|
||||||
always @(posedge muxclk, posedge muxlsron)
|
|
||||||
if (muxlsron)
|
|
||||||
Q <= srval;
|
|
||||||
else if (muxce)
|
|
||||||
Q <= DI;
|
|
||||||
end else begin
|
|
||||||
always @(posedge muxclk)
|
|
||||||
if (muxlsron)
|
|
||||||
Q <= srval;
|
|
||||||
else if (muxce)
|
|
||||||
Q <= DI;
|
|
||||||
end
|
|
||||||
end else if (REGMODE == "LATCH") begin
|
|
||||||
ERROR_UNSUPPORTED_FF_MODE error();
|
|
||||||
end else begin
|
|
||||||
ERROR_UNKNOWN_FF_MODE error();
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
/* For consistency with ECP5; represents F0/F1 => OFX0 mux in a slice. */
|
|
||||||
module PFUMX (input ALUT, BLUT, C0, output Z);
|
|
||||||
assign Z = C0 ? ALUT : BLUT;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
/* For consistency with ECP5; represents FXA/FXB => OFX1 mux in a slice. */
|
|
||||||
module L6MUX21 (input D0, D1, SD, output Z);
|
|
||||||
assign Z = SD ? D1 : D0;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
/* For consistency, input order matches TRELLIS_SLICE even though the BELs in
|
|
||||||
prjtrellis were filled in clockwise order from bottom left. */
|
|
||||||
module TRELLIS_SLICE #(
|
|
||||||
parameter MODE = "LOGIC",
|
|
||||||
parameter GSR = "ENABLED",
|
|
||||||
parameter SRMODE = "LSR_OVER_CE",
|
|
||||||
parameter CEMUX = "1",
|
|
||||||
parameter CLKMUX = "0",
|
|
||||||
parameter LSRMUX = "LSR",
|
|
||||||
parameter LSRONMUX = "LSRMUX",
|
|
||||||
parameter LUT0_INITVAL = 16'hFFFF,
|
|
||||||
parameter LUT1_INITVAL = 16'hFFFF,
|
|
||||||
parameter REGMODE = "FF",
|
|
||||||
parameter REG0_SD = "1",
|
|
||||||
parameter REG1_SD = "1",
|
|
||||||
parameter REG0_REGSET = "SET",
|
|
||||||
parameter REG1_REGSET = "SET",
|
|
||||||
parameter CCU2_INJECT1_0 = "YES",
|
|
||||||
parameter CCU2_INJECT1_1 = "YES",
|
|
||||||
parameter WREMUX = "INV"
|
|
||||||
) (
|
|
||||||
input A0, B0, C0, D0,
|
|
||||||
input A1, B1, C1, D1,
|
|
||||||
input M0, M1,
|
|
||||||
input FCI, FXA, FXB,
|
|
||||||
|
|
||||||
input CLK, LSR, CE,
|
|
||||||
input DI0, DI1,
|
|
||||||
|
|
||||||
input WD0, WD1,
|
|
||||||
input WAD0, WAD1, WAD2, WAD3,
|
|
||||||
input WRE, WCK,
|
|
||||||
|
|
||||||
output F0, Q0,
|
|
||||||
output F1, Q1,
|
|
||||||
output FCO, OFX0, OFX1,
|
|
||||||
|
|
||||||
output WDO0, WDO1, WDO2, WDO3,
|
|
||||||
output WADO0, WADO1, WADO2, WADO3
|
|
||||||
);
|
|
||||||
|
|
||||||
generate
|
|
||||||
if (MODE == "LOGIC") begin
|
|
||||||
L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
|
|
||||||
|
|
||||||
wire k0;
|
|
||||||
wire k1;
|
|
||||||
PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0));
|
|
||||||
|
|
||||||
LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0));
|
|
||||||
LUT4 #(.INIT(LUT1_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1));
|
|
||||||
|
|
||||||
assign F0 = k0;
|
|
||||||
assign F1 = k1;
|
|
||||||
end else if (MODE == "CCU2") begin
|
|
||||||
ERROR_UNSUPPORTED_SLICE_MODE error();
|
|
||||||
end else if (MODE == "DPRAM") begin
|
|
||||||
ERROR_UNSUPPORTED_SLICE_MODE error();
|
|
||||||
end else begin
|
|
||||||
ERROR_UNKNOWN_SLICE_MODE error();
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
/* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F
|
|
||||||
outputs (in other words, feeds back into TRELLIS_SLICE). */
|
|
||||||
wire di0 = (REG0_SD == "1") ? DI0 : M0;
|
|
||||||
wire di1 = (REG1_SD == "1") ? DI1 : M1;
|
|
||||||
|
|
||||||
TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
|
|
||||||
.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),
|
|
||||||
.REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0));
|
|
||||||
TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
|
|
||||||
.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
|
|
||||||
.REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
module TRELLIS_IO #(
|
|
||||||
parameter DIR = "INPUT"
|
|
||||||
) (
|
|
||||||
(* iopad_external_pin *)
|
|
||||||
inout B,
|
|
||||||
input I, T,
|
|
||||||
output O
|
|
||||||
);
|
|
||||||
generate
|
|
||||||
if (DIR == "INPUT") begin
|
|
||||||
assign O = B;
|
|
||||||
end else if (DIR == "OUTPUT") begin
|
|
||||||
assign B = T ? 1'bz : I;
|
|
||||||
end else if (DIR == "BIDIR") begin
|
|
||||||
assign B = T ? 1'bz : I;
|
|
||||||
assign O = B;
|
|
||||||
end else begin
|
|
||||||
ERROR_UNKNOWN_IO_MODE error();
|
|
||||||
end
|
|
||||||
endgenerate
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* abc9_box, lib_whitebox *)
|
|
||||||
module TRELLIS_DPR16X4 (
|
|
||||||
input [3:0] DI,
|
|
||||||
input [3:0] WAD,
|
|
||||||
input WRE,
|
|
||||||
input WCK,
|
|
||||||
input [3:0] RAD,
|
|
||||||
output [3:0] DO
|
|
||||||
);
|
|
||||||
parameter WCKMUX = "WCK";
|
|
||||||
parameter WREMUX = "WRE";
|
|
||||||
parameter [63:0] INITVAL = 64'h0000000000000000;
|
|
||||||
|
|
||||||
reg [3:0] mem[15:0];
|
|
||||||
|
|
||||||
integer i;
|
|
||||||
initial begin
|
|
||||||
for (i = 0; i < 16; i = i + 1)
|
|
||||||
mem[i] <= INITVAL[4*i +: 4];
|
|
||||||
end
|
|
||||||
|
|
||||||
wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
|
|
||||||
|
|
||||||
reg muxwre;
|
|
||||||
always @(*)
|
|
||||||
case (WREMUX)
|
|
||||||
"1": muxwre = 1'b1;
|
|
||||||
"0": muxwre = 1'b0;
|
|
||||||
"INV": muxwre = ~WRE;
|
|
||||||
default: muxwre = WRE;
|
|
||||||
endcase
|
|
||||||
|
|
||||||
always @(posedge muxwck)
|
|
||||||
if (muxwre)
|
|
||||||
mem[WAD] <= DI;
|
|
||||||
|
|
||||||
assign DO = mem[RAD];
|
|
||||||
|
|
||||||
specify
|
|
||||||
// TODO
|
|
||||||
(RAD *> DO) = 0;
|
|
||||||
endspecify
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* abc9_box, lib_whitebox *)
|
|
||||||
module DPR16X4C (
|
|
||||||
input [3:0] DI,
|
|
||||||
input WCK, WRE,
|
|
||||||
input [3:0] RAD,
|
|
||||||
input [3:0] WAD,
|
|
||||||
output [3:0] DO
|
|
||||||
);
|
|
||||||
parameter INITVAL = "0x0000000000000000";
|
|
||||||
|
|
||||||
function [63:0] convert_initval;
|
|
||||||
input [143:0] hex_initval;
|
|
||||||
reg done;
|
|
||||||
reg [63:0] temp;
|
|
||||||
reg [7:0] char;
|
|
||||||
integer i;
|
|
||||||
begin
|
|
||||||
done = 1'b0;
|
|
||||||
temp = 0;
|
|
||||||
for (i = 0; i < 16; i = i + 1) begin
|
|
||||||
if (!done) begin
|
|
||||||
char = hex_initval[8*i +: 8];
|
|
||||||
if (char == "x") begin
|
|
||||||
done = 1'b1;
|
|
||||||
end else begin
|
|
||||||
if (char >= "0" && char <= "9")
|
|
||||||
temp[4*i +: 4] = char - "0";
|
|
||||||
else if (char >= "A" && char <= "F")
|
|
||||||
temp[4*i +: 4] = 10 + char - "A";
|
|
||||||
else if (char >= "a" && char <= "f")
|
|
||||||
temp[4*i +: 4] = 10 + char - "a";
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end
|
|
||||||
convert_initval = temp;
|
|
||||||
end
|
|
||||||
endfunction
|
|
||||||
|
|
||||||
localparam conv_initval = convert_initval(INITVAL);
|
|
||||||
|
|
||||||
reg [3:0] ram[0:15];
|
|
||||||
integer i;
|
|
||||||
initial begin
|
|
||||||
for (i = 0; i < 15; i = i + 1) begin
|
|
||||||
ram[i] <= conv_initval[4*i +: 4];
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @(posedge WCK)
|
|
||||||
if (WRE)
|
|
||||||
ram[WAD] <= DI;
|
|
||||||
|
|
||||||
assign DO = ram[RAD];
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
// ---------------------------------------
|
|
||||||
(* lib_whitebox *)
|
|
||||||
module CCU2D (
|
|
||||||
input CIN,
|
|
||||||
input A0, B0, C0, D0, A1, B1, C1, D1,
|
|
||||||
output S0, S1,
|
|
||||||
output COUT
|
|
||||||
);
|
|
||||||
parameter [15:0] INIT0 = 16'h0000;
|
|
||||||
parameter [15:0] INIT1 = 16'h0000;
|
|
||||||
parameter INJECT1_0 = "YES";
|
|
||||||
parameter INJECT1_1 = "YES";
|
|
||||||
|
|
||||||
// First half
|
|
||||||
wire LUT4_0, LUT2_0;
|
|
||||||
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
|
|
||||||
LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
|
|
||||||
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
|
|
||||||
assign S0 = LUT4_0 ^ gated_cin_0;
|
|
||||||
|
|
||||||
wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
|
|
||||||
wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
|
|
||||||
|
|
||||||
// Second half
|
|
||||||
wire LUT4_1, LUT2_1;
|
|
||||||
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
|
|
||||||
LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
|
|
||||||
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
|
|
||||||
assign S1 = LUT4_1 ^ gated_cin_1;
|
|
||||||
|
|
||||||
wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
|
|
||||||
assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
(* blackbox *)
|
|
||||||
module DP8KC(
|
|
||||||
input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
|
|
||||||
input ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
|
|
||||||
input CEA, OCEA, CLKA, WEA, RSTA,
|
|
||||||
input CSA2, CSA1, CSA0,
|
|
||||||
output DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
|
|
||||||
|
|
||||||
input DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
|
|
||||||
input ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
|
|
||||||
input CEB, OCEB, CLKB, WEB, RSTB,
|
|
||||||
input CSB2, CSB1, CSB0,
|
|
||||||
output DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
|
|
||||||
);
|
|
||||||
parameter DATA_WIDTH_A = 9;
|
|
||||||
parameter DATA_WIDTH_B = 9;
|
|
||||||
|
|
||||||
parameter REGMODE_A = "NOREG";
|
|
||||||
parameter REGMODE_B = "NOREG";
|
|
||||||
|
|
||||||
parameter RESETMODE = "SYNC";
|
|
||||||
parameter ASYNC_RESET_RELEASE = "SYNC";
|
|
||||||
|
|
||||||
parameter CSDECODE_A = "0b000";
|
|
||||||
parameter CSDECODE_B = "0b000";
|
|
||||||
|
|
||||||
parameter WRITEMODE_A = "NORMAL";
|
|
||||||
parameter WRITEMODE_B = "NORMAL";
|
|
||||||
|
|
||||||
parameter GSR = "ENABLED";
|
|
||||||
parameter INIT_DATA = "STATIC";
|
|
||||||
|
|
||||||
parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
`ifndef NO_INCLUDES
|
|
||||||
|
|
||||||
`include "cells_io.vh"
|
|
||||||
|
|
||||||
`endif
|
|
||||||
|
|
@ -1,297 +0,0 @@
|
||||||
/*
|
|
||||||
* yosys -- Yosys Open SYnthesis Suite
|
|
||||||
*
|
|
||||||
* Copyright (C) 2020 William D. Jones <wjones@wdj-consulting.com>
|
|
||||||
*
|
|
||||||
* Permission to use, copy, modify, and/or distribute this software for any
|
|
||||||
* purpose with or without fee is hereby granted, provided that the above
|
|
||||||
* copyright notice and this permission notice appear in all copies.
|
|
||||||
*
|
|
||||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
||||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
||||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
||||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
||||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
||||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
||||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include "kernel/register.h"
|
|
||||||
#include "kernel/celltypes.h"
|
|
||||||
#include "kernel/rtlil.h"
|
|
||||||
#include "kernel/log.h"
|
|
||||||
|
|
||||||
USING_YOSYS_NAMESPACE
|
|
||||||
PRIVATE_NAMESPACE_BEGIN
|
|
||||||
|
|
||||||
struct SynthMachXO2Pass : public ScriptPass
|
|
||||||
{
|
|
||||||
SynthMachXO2Pass() : ScriptPass("synth_machxo2", "synthesis for MachXO2 FPGAs. This work is experimental.") { }
|
|
||||||
|
|
||||||
void help() override
|
|
||||||
{
|
|
||||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
||||||
log("\n");
|
|
||||||
log(" synth_machxo2 [options]\n");
|
|
||||||
log("\n");
|
|
||||||
log("This command runs synthesis for MachXO2 FPGAs.\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -top <module>\n");
|
|
||||||
log(" use the specified module as top module\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -blif <file>\n");
|
|
||||||
log(" write the design to the specified BLIF file. writing of an output file\n");
|
|
||||||
log(" is omitted if this parameter is not specified.\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -edif <file>\n");
|
|
||||||
log(" write the design to the specified EDIF file. writing of an output file\n");
|
|
||||||
log(" is omitted if this parameter is not specified.\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -json <file>\n");
|
|
||||||
log(" write the design to the specified JSON file. writing of an output file\n");
|
|
||||||
log(" is omitted if this parameter is not specified.\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -run <from_label>:<to_label>\n");
|
|
||||||
log(" only run the commands between the labels (see below). an empty\n");
|
|
||||||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
|
||||||
log(" synonymous to the end of the command list.\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -nobram\n");
|
|
||||||
log(" do not use block RAM cells in output netlist\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -nolutram\n");
|
|
||||||
log(" do not use LUT RAM cells in output netlist\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -noflatten\n");
|
|
||||||
log(" do not flatten design before synthesis\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -noiopad\n");
|
|
||||||
log(" do not insert IO buffers\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -ccu2\n");
|
|
||||||
log(" use CCU2 cells in output netlist\n");
|
|
||||||
log("\n");
|
|
||||||
log(" -vpr\n");
|
|
||||||
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
|
|
||||||
log(" (this feature is experimental and incomplete)\n");
|
|
||||||
log("\n");
|
|
||||||
log("\n");
|
|
||||||
log("The following commands are executed by this synthesis command:\n");
|
|
||||||
help_script();
|
|
||||||
log("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
string top_opt, blif_file, edif_file, json_file;
|
|
||||||
bool ccu2, nobram, nolutram, flatten, vpr, noiopad;
|
|
||||||
|
|
||||||
void clear_flags() override
|
|
||||||
{
|
|
||||||
top_opt = "-auto-top";
|
|
||||||
blif_file = "";
|
|
||||||
edif_file = "";
|
|
||||||
json_file = "";
|
|
||||||
ccu2 = false;
|
|
||||||
nobram = false;
|
|
||||||
nolutram = false;
|
|
||||||
flatten = true;
|
|
||||||
vpr = false;
|
|
||||||
noiopad = false;
|
|
||||||
}
|
|
||||||
|
|
||||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
||||||
{
|
|
||||||
string run_from, run_to;
|
|
||||||
clear_flags();
|
|
||||||
|
|
||||||
size_t argidx;
|
|
||||||
for (argidx = 1; argidx < args.size(); argidx++)
|
|
||||||
{
|
|
||||||
if (args[argidx] == "-top" && argidx+1 < args.size()) {
|
|
||||||
top_opt = "-top " + args[++argidx];
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-blif" && argidx+1 < args.size()) {
|
|
||||||
blif_file = args[++argidx];
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
|
|
||||||
edif_file = args[++argidx];
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-json" && argidx+1 < args.size()) {
|
|
||||||
json_file = args[++argidx];
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-run" && argidx+1 < args.size()) {
|
|
||||||
size_t pos = args[argidx+1].find(':');
|
|
||||||
if (pos == std::string::npos)
|
|
||||||
break;
|
|
||||||
run_from = args[++argidx].substr(0, pos);
|
|
||||||
run_to = args[argidx].substr(pos+1);
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-flatten") {
|
|
||||||
flatten = true;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-noflatten") {
|
|
||||||
flatten = false;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-nobram") {
|
|
||||||
nobram = true;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-nolutram") {
|
|
||||||
nolutram = true;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-noiopad") {
|
|
||||||
noiopad = true;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-ccu2") {
|
|
||||||
ccu2 = true;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (args[argidx] == "-vpr") {
|
|
||||||
vpr = true;
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
extra_args(args, argidx, design);
|
|
||||||
|
|
||||||
if (!design->full_selection())
|
|
||||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
|
||||||
|
|
||||||
log_header(design, "Executing SYNTH_MACHXO2 pass.\n");
|
|
||||||
log_push();
|
|
||||||
|
|
||||||
run_script(design, run_from, run_to);
|
|
||||||
|
|
||||||
log_pop();
|
|
||||||
}
|
|
||||||
|
|
||||||
void script() override
|
|
||||||
{
|
|
||||||
if (check_label("begin"))
|
|
||||||
{
|
|
||||||
run("read_verilog -lib -icells +/machxo2/cells_sim.v +/machxo2/cells_bb.v");
|
|
||||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("flatten", "(unless -noflatten)"))
|
|
||||||
{
|
|
||||||
if (flatten || help_mode) {
|
|
||||||
run("proc");
|
|
||||||
run("flatten");
|
|
||||||
run("tribuf -logic");
|
|
||||||
run("deminout");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("coarse"))
|
|
||||||
{
|
|
||||||
run("synth -run coarse");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("map_ram"))
|
|
||||||
{
|
|
||||||
std::string args = "";
|
|
||||||
if (nobram)
|
|
||||||
args += " -no-auto-block";
|
|
||||||
if (nolutram)
|
|
||||||
args += " -no-auto-distributed";
|
|
||||||
if (help_mode)
|
|
||||||
args += " [-no-auto-block] [-no-auto-distributed]";
|
|
||||||
run("memory_libmap -lib +/machxo2/lutrams.txt -lib +/machxo2/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
|
|
||||||
run("techmap -map +/machxo2/lutrams_map.v -map +/machxo2/brams_map.v");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("fine"))
|
|
||||||
{
|
|
||||||
run("opt -fast -mux_undef -undriven -fine");
|
|
||||||
run("memory_map");
|
|
||||||
run("opt -undriven -fine");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("map_gates", "(unless -noiopad)"))
|
|
||||||
{
|
|
||||||
if (!ccu2)
|
|
||||||
run("techmap");
|
|
||||||
else
|
|
||||||
run("techmap -map +/techmap.v -map +/machxo2/arith_map.v");
|
|
||||||
if (!noiopad || help_mode)
|
|
||||||
{
|
|
||||||
run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')");
|
|
||||||
run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]");
|
|
||||||
run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("map_ffs"))
|
|
||||||
{
|
|
||||||
run("opt_clean");
|
|
||||||
std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
|
|
||||||
run("dfflegalize" + dfflegalize_args);
|
|
||||||
run("techmap -D NO_LUT -map +/machxo2/cells_map.v");
|
|
||||||
run("opt_expr -undriven -mux_undef");
|
|
||||||
run("simplemap");
|
|
||||||
run("lattice_gsr");
|
|
||||||
run("attrmvcp -copy -attr syn_useioff");
|
|
||||||
run("opt_clean");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("map_luts"))
|
|
||||||
{
|
|
||||||
run("abc -lut 4 -dress");
|
|
||||||
run("clean");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("map_cells"))
|
|
||||||
{
|
|
||||||
run("techmap -map +/machxo2/cells_map.v");
|
|
||||||
run("clean");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("check"))
|
|
||||||
{
|
|
||||||
run("hierarchy -check");
|
|
||||||
run("stat");
|
|
||||||
run("blackbox =A:whitebox");
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("blif"))
|
|
||||||
{
|
|
||||||
if (!blif_file.empty() || help_mode) {
|
|
||||||
if (vpr || help_mode) {
|
|
||||||
run(stringf("opt_clean -purge"),
|
|
||||||
" (vpr mode)");
|
|
||||||
run(stringf("write_blif -attr -cname -conn -param %s",
|
|
||||||
help_mode ? "<file-name>" : blif_file.c_str()),
|
|
||||||
" (vpr mode)");
|
|
||||||
}
|
|
||||||
if (!vpr)
|
|
||||||
run(stringf("write_blif -gates -attr -param %s",
|
|
||||||
help_mode ? "<file-name>" : blif_file.c_str()),
|
|
||||||
" (non-vpr mode)");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("edif"))
|
|
||||||
{
|
|
||||||
if (!edif_file.empty() || help_mode)
|
|
||||||
run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
|
|
||||||
}
|
|
||||||
|
|
||||||
if (check_label("json"))
|
|
||||||
{
|
|
||||||
if (!json_file.empty() || help_mode)
|
|
||||||
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} SynthMachXO2Pass;
|
|
||||||
|
|
||||||
PRIVATE_NAMESPACE_END
|
|
||||||
Loading…
Reference in New Issue