mirror of https://github.com/YosysHQ/yosys.git
fmt: rudimentary %m support (= %l)
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@ -291,6 +291,9 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
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} else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") {
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} else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") {
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i++;
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i++;
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part.str += module_name.str();
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part.str += module_name.str();
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} else if (fmt.substr(i, 2) == "%m" || fmt.substr(i, 2) == "%M") {
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i++;
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part.str += module_name.str();
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} else {
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} else {
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if (!part.str.empty()) {
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if (!part.str.empty()) {
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part.type = FmtPart::STRING;
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part.type = FmtPart::STRING;
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@ -0,0 +1,12 @@
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module top;
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mid mid_uut ();
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endmodule
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module mid ();
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bot bot_uut ();
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endmodule
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module bot ();
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initial $display("%%l: %l\n%%m: %m");
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always $display("%%l: %l\n%%m: %m");
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endmodule
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@ -0,0 +1,10 @@
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#include <iostream>
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#include "yosys-display_lm.cc"
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int main()
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{
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cxxrtl_design::p_top uut;
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uut.step();
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return 0;
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}
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@ -53,3 +53,12 @@ ${CXX:-g++} -o yosys-always_full -I../.. always_full_tb.cc
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iverilog -o iverilog-always_full always_full.v always_full_tb.v
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iverilog -o iverilog-always_full always_full.v always_full_tb.v
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./iverilog-always_full | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >iverilog-always_full.log
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./iverilog-always_full | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >iverilog-always_full.log
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diff iverilog-always_full.log yosys-always_full.log
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diff iverilog-always_full.log yosys-always_full.log
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../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log
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../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc"
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${CXX:-g++} -o yosys-display_lm_cc -I../.. display_lm_tb.cc
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./yosys-display_lm_cc >yosys-display_lm_cc.log
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for log in yosys-display_lm.log yosys-display_lm_cc.log; do
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grep "^%l: \\\\bot\$" "$log"
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grep "^%m: \\\\bot\$" "$log"
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done
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