riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

xilinx: Use INV instead of LUT1 when applicable

This commit is contained in:
Marcin Kościelnicki 2019-11-24 14:17:46 +01:00 committed by Marcin Kościelnicki
parent db2268703f
commit 7562e7304e
5 changed files with 14 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
techlibs/xilinx/lut_map.v
View File

@ -56,8 +56,12 @@ module \$lut (A, Y);
generate
if (WIDTH == 1) begin
if (P_LUT == 2'b01) begin
INV _TECHMAP_REPLACE_ (.O(Y), .I(A[0]));
end else begin
LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[0]));
end
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),

4
tests/arch/xilinx/adffs.ys
View File

@ -20,9 +20,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd adffn # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
select -assert-count 1 t:LUT1
select -assert-count 1 t:INV
select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
select -assert-none t:BUFG t:FDCE t:INV %% t:* %D
design -load read

4
tests/arch/xilinx/counter.ys
View File

@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDCE
select -assert-count 1 t:LUT1
select -assert-count 1 t:INV
select -assert-count 7 t:MUXCY
select -assert-count 8 t:XORCY
select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D
select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D

4
tests/arch/xilinx/latches.ys
View File

@ -18,9 +18,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalen
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
select -assert-count 1 t:LUT1
select -assert-count 1 t:INV
select -assert-none t:LDCE t:LUT1 %% t:* %D
select -assert-none t:LDCE t:INV %% t:* %D
design -load read

4
tests/arch/xilinx/logic.ys
View File

@ -5,7 +5,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT1
select -assert-count 1 t:INV
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D