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Add missing is_signed to type_atom 

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
This commit is contained in:
Kamil Rakoczy 2021-02-11 12:53:07 +01:00
parent eff18a2b15
commit 7533534429
2 changed files with 23 additions and 4 deletions
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8
frontends/verilog/verilog_parser.y
View File

@ -1491,10 +1491,10 @@ enum_base_type: type_atom type_signing
| %empty { astbuf1->is_reg = true; addRange(astbuf1); }
;
type_atom: TOK_INTEGER { astbuf1->is_reg = true; addRange(astbuf1); } // 4-state signed
| TOK_INT { astbuf1->is_reg = true; addRange(astbuf1); } // 2-state signed
| TOK_SHORTINT { astbuf1->is_reg = true; addRange(astbuf1, 15, 0); } // 2-state signed
| TOK_BYTE { astbuf1->is_reg = true; addRange(astbuf1, 7, 0); } // 2-state signed
type_atom: TOK_INTEGER { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 4-state signed
| TOK_INT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1); } // 2-state signed
| TOK_SHORTINT { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 15, 0); } // 2-state signed
| TOK_BYTE { astbuf1->is_reg = true; astbuf1->is_signed = true; addRange(astbuf1, 7, 0); } // 2-state signed
;
type_vec: TOK_REG { astbuf1->is_reg = true; } // unsigned

19
tests/verilog/atom_type_signedness.ys Normal file
View File

@ -0,0 +1,19 @@
read_verilog -dump_ast1 -dump_ast2 -sv <<EOT
module dut();
enum integer { uInteger = -10 } a;
enum int { uInt = -11 } b;
enum shortint { uShortInt = -12 } c;
enum byte { uByte = -13 } d;
always_comb begin
assert(-10 == uInteger);
assert(-11 == uInt);
assert(-12 == uShortInt);
assert(-13 == uByte);
end
endmodule
EOT
hierarchy; proc; opt
select -module dut
sat -verify -seq 1 -tempinduct -prove-asserts -show-all