riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9_ops: -prep_box, to be called once

This commit is contained in:
Eddie Hung 2020-02-11 08:54:13 -08:00
parent 5643c1b8c5
commit 74f49b1f55
3 changed files with 50 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
passes/techmap/abc9.cc
View File

@ -192,7 +192,7 @@ struct Abc9Pass : public ScriptPass
cleanup = true; cleanup = true;
lut_mode = false; lut_mode = false;
maxlut = 0; maxlut = 0;
box_file.clear(); box_file = "(null)";
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -285,6 +285,10 @@ struct Abc9Pass : public ScriptPass
run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)"); run("abc9_ops -prep_lut <maxlut>", "(skip if -lut or -luts)");
else if (!lut_mode) else if (!lut_mode)
run(stringf("abc9_ops -prep_lut %d", maxlut)); run(stringf("abc9_ops -prep_lut %d", maxlut));
if (help_mode)
run("abc9_ops -prep_box [<-box>|(null)]");
else
run(stringf("abc9_ops -prep_box %s", box_file.c_str()));
run("select -set abc9_holes A:abc9_holes"); run("select -set abc9_holes A:abc9_holes");
run("flatten -wb @abc9_holes"); run("flatten -wb @abc9_holes");
run("techmap @abc9_holes"); run("techmap @abc9_holes");
@ -299,7 +303,7 @@ struct Abc9Pass : public ScriptPass
if (help_mode) { if (help_mode) {
run("foreach module in selection"); run("foreach module in selection");
run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')"); run(" abc9_ops -write_lut <abc-temp-dir>/input.lut", "(skip if '-lut' or '-luts')");
run(" abc9_ops -write_box [<value from -box>|(null)] <abc-temp-dir>/input.box"); run(" abc9_ops -write_box <abc-temp-dir>/input.box");
run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig"); run(" write_xaiger -map <abc-temp-dir>/input.sym <abc-temp-dir>/input.xaig");
run(" abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box"); run(" abc9_exe [options] -cwd <abc-temp-dir> [-lut <abc-temp-dir>/input.lut] -box <abc-temp-dir>/input.box");
run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig"); run(" read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig");
@ -329,10 +333,7 @@ struct Abc9Pass : public ScriptPass
if (!lut_mode) if (!lut_mode)
run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str())); run(stringf("abc9_ops -write_lut %s/input.lut", tempdir_name.c_str()));
if (box_file.empty()) run(stringf("abc9_ops -write_box %s/input.box", tempdir_name.c_str()));
run(stringf("abc9_ops -write_box (null) %s/input.box", tempdir_name.c_str()));
else
run(stringf("abc9_ops -write_box %s %s/input.box", box_file.c_str(), tempdir_name.c_str()));
run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str())); run(stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs"); int num_outputs = active_design->scratchpad_get_int("write_xaiger.num_outputs");

86
passes/techmap/abc9_ops.cc
View File

@ -464,7 +464,6 @@ void prep_delays(RTLIL::Design *design)
cells.emplace_back(cell); cells.emplace_back(cell);
} }
delays.clear();
for (auto cell : cells) { for (auto cell : cells) {
RTLIL::Module* inst_module = module->design->module(cell->type); RTLIL::Module* inst_module = module->design->module(cell->type);
log_assert(inst_module); log_assert(inst_module);
@ -515,17 +514,6 @@ void prep_delays(RTLIL::Design *design)
} }
} }
} }
std::stringstream ss;
bool first = true;
for (auto d : delays) {
if (first)
first = false;
else
ss << " ";
ss << d;
}
module->attributes[ID(abc9_delays)] = ss.str();
} }
int flops_id = ABC9_FLOPS_BASE_ID; int flops_id = ABC9_FLOPS_BASE_ID;
@ -559,7 +547,14 @@ void prep_delays(RTLIL::Design *design)
// Last input is 'abc9_ff.Q' // Last input is 'abc9_ff.Q'
ss << " 0" << std::endl << std::endl; ss << " 0" << std::endl << std::endl;
} }
design->scratchpad_set_string("abc9_ops.box.flops", ss.str()); design->scratchpad_set_string("abc9_ops.box_library.flops", ss.str());
ss.str("");
for (const int d : delays) {
ss << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
ss << d << std::endl;
}
design->scratchpad_set_string("abc9_ops.box_library.delays", ss.str());
} }
void prep_lut(RTLIL::Design *design, int maxlut) void prep_lut(RTLIL::Design *design, int maxlut)
@ -612,33 +607,31 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
ofs.close(); ofs.close();
} }
void write_box(RTLIL::Module *module, const std::string &src, const std::string &dst) { void prep_box(RTLIL::Design *design, const std::string &src)
std::ofstream ofs(dst); {
log_assert(ofs.is_open()); std::stringstream ss;
// Since ABC can only accept one box file, we have to copy // Since ABC can only accept one box file, we have to copy
// over the existing box file // over the existing box file
if (src != "(null)") { if (src != "(null)") {
std::ifstream ifs(src); std::ifstream ifs(src);
ofs << ifs.rdbuf() << std::endl; log_assert(ifs.is_open());
ss << ifs.rdbuf() << std::endl;
ifs.close(); ifs.close();
} }
ofs << module->design->scratchpad_get_string("abc9_ops.box.flops"); ss << design->scratchpad_get_string("abc9_ops.box_library.flops", ss.str());
ss << design->scratchpad_get_string("abc9_ops.box_library.delays", ss.str());
auto it = module->attributes.find(ID(abc9_delays)); design->scratchpad_set_string("abc9_ops.box_library", ss.str());
if (it != module->attributes.end()) { }
for (const auto &tok : split_tokens(it->second.decode_string())) {
int d = atoi(tok.c_str());
ofs << "$__ABC9_DELAY@" << d << " " << ABC9_DELAY_BASE_ID + d << " 0 1 1" << std::endl;
ofs << d << std::endl;
}
module->attributes.erase(it);
}
void write_box(RTLIL::Module *module, const std::string &dst) {
std::ofstream ofs(dst);
log_assert(ofs.is_open());
ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
// ABC expects at least one box
if (ofs.tellp() == 0) if (ofs.tellp() == 0)
ofs << "(dummy) 1 0 0 0"; ofs << "(dummy) 1 0 0 0";
ofs.close(); ofs.close();
} }
@ -1056,11 +1049,14 @@ struct Abc9OpsPass : public Pass {
log(" pre-compute the lut library.\n"); log(" pre-compute the lut library.\n");
log("\n"); log("\n");
log(" -write_lut <dst>\n"); log(" -write_lut <dst>\n");
log(" TODO.\n"); log(" write the pre-computed lut library to <dst>.\n");
log("\n"); log("\n");
log(" -write_box (<src>|(null)) <dst>\n"); log(" -prep_box <src>\n");
log(" copy the existing box file from <src> (skip if '(null)') and append any\n"); log(" pre-compute the box library. copy the existing box file from <src> (skip\n");
log(" new box definitions.\n"); log(" if '(null)').\n");
log("\n");
log(" -write_box <dst>\n");
log(" write the pre-computed box library to <dst>.\n");
log("\n"); log("\n");
log(" -reintegrate\n"); log(" -reintegrate\n");
log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n"); log(" for each selected module, re-intergrate the module '<module-name>$abc9'\n");
@ -1082,7 +1078,7 @@ struct Abc9OpsPass : public Pass {
bool dff_mode = false; bool dff_mode = false;
std::string write_lut_dst; std::string write_lut_dst;
int maxlut = 0; int maxlut = 0;
std::string write_box_src, write_box_dst; std::string prep_box_src, write_box_dst;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
@ -1112,18 +1108,21 @@ struct Abc9OpsPass : public Pass {
maxlut = atoi(args[++argidx].c_str()); maxlut = atoi(args[++argidx].c_str());
continue; continue;
} }
if (arg == "-maxlut" && argidx+1 < args.size()) {
continue;
}
if (arg == "-write_lut" && argidx+1 < args.size()) { if (arg == "-write_lut" && argidx+1 < args.size()) {
write_lut_dst = args[++argidx]; write_lut_dst = args[++argidx];
rewrite_filename(write_lut_dst); rewrite_filename(write_lut_dst);
continue; continue;
} }
if (arg == "-maxlut" && argidx+1 < args.size()) { if (arg == "-prep_box" && argidx+1 < args.size()) {
prep_box_src = args[++argidx];
rewrite_filename(prep_box_src);
continue; continue;
} }
if (arg == "-write_box" && argidx+2 < args.size()) { if (arg == "-write_box" && argidx+1 < args.size()) {
write_box_src = args[++argidx];
write_box_dst = args[++argidx]; write_box_dst = args[++argidx];
rewrite_filename(write_box_src);
rewrite_filename(write_box_dst); rewrite_filename(write_box_dst);
continue; continue;
} }
@ -1139,21 +1138,20 @@ struct Abc9OpsPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode)) if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || !prep_box_src.empty() || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut}, -write_{lut,box}, -reintegrate must be specified.\n"); log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
if (dff_mode && !prep_xaiger_mode) if (dff_mode && !prep_xaiger_mode)
log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n"); log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
if (maxlut && !write_lut_dst.empty())
log_cmd_error("'-maxlut' option is only relevant for -prep_lut.\n");
if (check_mode) if (check_mode)
check(design); check(design);
if (prep_delays_mode) if (prep_delays_mode)
prep_delays(design); prep_delays(design);
if (prep_lut_mode) if (prep_lut_mode)
prep_lut(design, maxlut); prep_lut(design, maxlut);
if (!prep_box_src.empty())
prep_box(design, prep_box_src);
for (auto mod : design->selected_modules()) { for (auto mod : design->selected_modules()) {
if (mod->get_bool_attribute("\\abc9_holes")) if (mod->get_bool_attribute("\\abc9_holes"))
@ -1170,7 +1168,7 @@ struct Abc9OpsPass : public Pass {
if (!write_lut_dst.empty()) if (!write_lut_dst.empty())
write_lut(mod, write_lut_dst); write_lut(mod, write_lut_dst);
if (!write_box_dst.empty()) if (!write_box_dst.empty())
write_box(mod, write_box_src, write_box_dst); write_box(mod, write_box_dst);
if (mark_scc_mode) if (mark_scc_mode)
mark_scc(mod); mark_scc(mod);
if (prep_dff_mode) if (prep_dff_mode)

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -627,7 +627,7 @@ struct SynthXilinxPass : public ScriptPass
else else
abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str()); abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str());
if (nowidelut) if (nowidelut)
abc9_opts += stringf(" -maxlut %d", lut_size_s); abc9_opts += stringf(" -maxlut %d", lut_size);
if (dff_mode) if (dff_mode)
abc9_opts += " -dff"; abc9_opts += " -dff";
run("abc9" + abc9_opts); run("abc9" + abc9_opts);