mirror of https://github.com/YosysHQ/yosys.git
Add some cleanup code to memory_nordff
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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9a946c207f
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@ -61,15 +61,17 @@ struct MemoryNordffPass : public Pass {
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SigSpec rd_addr = cell->getPort("\\RD_ADDR");
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SigSpec rd_data = cell->getPort("\\RD_DATA");
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SigSpec rd_clk = cell->getPort("\\RD_CLK");
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SigSpec rd_en = cell->getPort("\\RD_EN");
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Const rd_clk_enable = cell->getParam("\\RD_CLK_ENABLE");
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Const rd_clk_polarity = cell->getParam("\\RD_CLK_POLARITY");
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for (int i = 0; i < rd_ports; i++)
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{
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bool clk_enable = rd_clk_enable[i] == State::S1;
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if (!clk_enable)
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continue;
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if (clk_enable)
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{
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bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1;
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bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1;
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@ -98,12 +100,20 @@ struct MemoryNordffPass : public Pass {
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log("Extracted %s FF from read port %d of %s.%s: %s\n", transparent ? "addr" : "data",
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i, log_id(module), log_id(cell), log_id(c));
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}
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rd_en[i] = State::S1;
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rd_clk[i] = State::S0;
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rd_clk_enable[i] = State::S0;
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rd_clk_polarity[i] = State::S1;
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}
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cell->setPort("\\RD_ADDR", rd_addr);
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cell->setPort("\\RD_DATA", rd_data);
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cell->setPort("\\RD_CLK", rd_clk);
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cell->setPort("\\RD_EN", rd_en);
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cell->setParam("\\RD_CLK_ENABLE", rd_clk_enable);
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cell->setParam("\\RD_CLK_POLARITY", rd_clk_polarity);
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}
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}
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} MemoryNordffPass;
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