mirror of https://github.com/YosysHQ/yosys.git
Fix xilinx_dsp for unsigned extensions
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@ -277,7 +277,9 @@ match postAdd
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index <SigBit> port(postAdd, AB)[0] === sigP[0]
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index <SigBit> port(postAdd, AB)[0] === sigP[0]
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filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
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filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
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filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
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filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
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filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP))
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// Check that remainder of AB is a sign-extension
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define <bool> AB_SIGNED (param(postAdd, AB == \A ? \A_SIGNED : \B_SIGNED).as_bool())
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filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(AB_SIGNED ? sigP[GetSize(sigP)-1] : State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
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set postAddAB AB
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set postAddAB AB
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optional
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optional
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endmatch
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endmatch
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