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recover_reduce: Reindent using tabs

This commit is contained in:
Robert Ou 2017-08-27 02:12:41 -07:00
parent 8a5887464c
commit 74d0f17fd4
1 changed files with 164 additions and 164 deletions
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328
passes/techmap/recover_reduce.cc
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@ -24,196 +24,196 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
struct RecoverReduceCorePass : public Pass { struct RecoverReduceCorePass : public Pass {
enum GateType { enum GateType {
And, And,
Or, Or,
Xor Xor
}; };
RecoverReduceCorePass() : Pass("recover_reduce_core", "converts gate chains into $reduce_*") { } RecoverReduceCorePass() : Pass("recover_reduce_core", "converts gate chains into $reduce_*") { }
virtual void help() virtual void help()
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" recover_reduce_core\n"); log(" recover_reduce_core\n");
log("\n"); log("\n");
log("converts gate chains into $reduce_*\n"); log("converts gate chains into $reduce_*\n");
log("\n"); log("\n");
log("This performs the core step of the recover_reduce command. This step recognizes\n"); log("This performs the core step of the recover_reduce command. This step recognizes\n");
log("chains of gates found by the previous steps and converts these chains into one\n"); log("chains of gates found by the previous steps and converts these chains into one\n");
log("logical cell.\n"); log("logical cell.\n");
log("\n"); log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
(void)args; (void)args;
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
SigMap sigmap(module); SigMap sigmap(module);
// Index all of the nets in the module // Index all of the nets in the module
dict<SigBit, Cell*> sig_to_driver; dict<SigBit, Cell*> sig_to_driver;
dict<SigBit, pool<Cell*>> sig_to_sink; dict<SigBit, pool<Cell*>> sig_to_sink;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
{ {
if (cell->output(conn.first)) if (cell->output(conn.first))
for (auto bit : sigmap(conn.second)) for (auto bit : sigmap(conn.second))
sig_to_driver[bit] = cell; sig_to_driver[bit] = cell;
if (cell->input(conn.first)) if (cell->input(conn.first))
{ {
for (auto bit : sigmap(conn.second)) for (auto bit : sigmap(conn.second))
{ {
if (sig_to_sink.count(bit) == 0) if (sig_to_sink.count(bit) == 0)
sig_to_sink[bit] = pool<Cell*>(); sig_to_sink[bit] = pool<Cell*>();
sig_to_sink[bit].insert(cell); sig_to_sink[bit].insert(cell);
} }
} }
} }
} }
// Need to check if any wires connect to module ports // Need to check if any wires connect to module ports
pool<SigBit> port_sigs; pool<SigBit> port_sigs;
for (auto wire : module->selected_wires()) for (auto wire : module->selected_wires())
if (wire->port_input || wire->port_output) if (wire->port_input || wire->port_output)
for (auto bit : sigmap(wire)) for (auto bit : sigmap(wire))
port_sigs.insert(bit); port_sigs.insert(bit);
// Actual logic starts here // Actual logic starts here
pool<Cell*> consumed_cells; pool<Cell*> consumed_cells;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (consumed_cells.count(cell)) if (consumed_cells.count(cell))
continue; continue;
GateType gt; GateType gt;
if (cell->type == "$_AND_") if (cell->type == "$_AND_")
gt = GateType::And; gt = GateType::And;
else if (cell->type == "$_OR_") else if (cell->type == "$_OR_")
gt = GateType::Or; gt = GateType::Or;
else if (cell->type == "$_XOR_") else if (cell->type == "$_XOR_")
gt = GateType::Xor; gt = GateType::Xor;
else else
continue; continue;
log("Working on cell %s...\n", cell->name.c_str()); log("Working on cell %s...\n", cell->name.c_str());
// Go all the way to the sink // Go all the way to the sink
Cell* head_cell = cell; Cell* head_cell = cell;
Cell* x = cell; Cell* x = cell;
while (true) while (true)
{ {
if (!((x->type == "$_AND_" && gt == GateType::And) || if (!((x->type == "$_AND_" && gt == GateType::And) ||
(x->type == "$_OR_" && gt == GateType::Or) || (x->type == "$_OR_" && gt == GateType::Or) ||
(x->type == "$_XOR_" && gt == GateType::Xor))) (x->type == "$_XOR_" && gt == GateType::Xor)))
break; break;
head_cell = x; head_cell = x;
auto y = sigmap(x->getPort("\\Y")); auto y = sigmap(x->getPort("\\Y"));
log_assert(y.size() == 1); log_assert(y.size() == 1);
// Should only continue if there is one fanout back into a cell (not to a port) // Should only continue if there is one fanout back into a cell (not to a port)
if (sig_to_sink[y[0]].size() != 1) if (sig_to_sink[y[0]].size() != 1)
break; break;
x = *sig_to_sink[y[0]].begin(); x = *sig_to_sink[y[0]].begin();
} }
log(" Head cell is %s\n", head_cell->name.c_str()); log(" Head cell is %s\n", head_cell->name.c_str());
pool<Cell*> cur_supercell; pool<Cell*> cur_supercell;
std::deque<Cell*> bfs_queue = {head_cell}; std::deque<Cell*> bfs_queue = {head_cell};
while (bfs_queue.size()) while (bfs_queue.size())
{ {
Cell* x = bfs_queue.front(); Cell* x = bfs_queue.front();
bfs_queue.pop_front(); bfs_queue.pop_front();
cur_supercell.insert(x); cur_supercell.insert(x);
auto a = sigmap(x->getPort("\\A")); auto a = sigmap(x->getPort("\\A"));
log_assert(a.size() == 1); log_assert(a.size() == 1);
// Must have only one sink // Must have only one sink
// XXX: Check that it is indeed this node? // XXX: Check that it is indeed this node?
if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1) if (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1)
{ {
Cell* cell_a = sig_to_driver[a[0]]; Cell* cell_a = sig_to_driver[a[0]];
if (((cell_a->type == "$_AND_" && gt == GateType::And) || if (((cell_a->type == "$_AND_" && gt == GateType::And) ||
(cell_a->type == "$_OR_" && gt == GateType::Or) || (cell_a->type == "$_OR_" && gt == GateType::Or) ||
(cell_a->type == "$_XOR_" && gt == GateType::Xor))) (cell_a->type == "$_XOR_" && gt == GateType::Xor)))
{ {
// The cell here is the correct type, and it's definitely driving only // The cell here is the correct type, and it's definitely driving only
// this current cell. // this current cell.
bfs_queue.push_back(cell_a); bfs_queue.push_back(cell_a);
} }
} }
auto b = sigmap(x->getPort("\\B")); auto b = sigmap(x->getPort("\\B"));
log_assert(b.size() == 1); log_assert(b.size() == 1);
// Must have only one sink // Must have only one sink
// XXX: Check that it is indeed this node? // XXX: Check that it is indeed this node?
if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1) if (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1)
{ {
Cell* cell_b = sig_to_driver[b[0]]; Cell* cell_b = sig_to_driver[b[0]];
if (((cell_b->type == "$_AND_" && gt == GateType::And) || if (((cell_b->type == "$_AND_" && gt == GateType::And) ||
(cell_b->type == "$_OR_" && gt == GateType::Or) || (cell_b->type == "$_OR_" && gt == GateType::Or) ||
(cell_b->type == "$_XOR_" && gt == GateType::Xor))) (cell_b->type == "$_XOR_" && gt == GateType::Xor)))
{ {
// The cell here is the correct type, and it's definitely driving only // The cell here is the correct type, and it's definitely driving only
// this current cell. // this current cell.
bfs_queue.push_back(cell_b); bfs_queue.push_back(cell_b);
} }
} }
} }
log(" Cells:\n"); log(" Cells:\n");
for (auto x : cur_supercell) for (auto x : cur_supercell)
log(" %s\n", x->name.c_str()); log(" %s\n", x->name.c_str());
if (cur_supercell.size() > 1) if (cur_supercell.size() > 1)
{ {
// Worth it to create reduce cell // Worth it to create reduce cell
log(" Creating $reduce_* cell!\n"); log(" Creating $reduce_* cell!\n");
pool<SigBit> input_pool; pool<SigBit> input_pool;
pool<SigBit> input_pool_intermed; pool<SigBit> input_pool_intermed;
for (auto x : cur_supercell) for (auto x : cur_supercell)
{ {
input_pool.insert(sigmap(x->getPort("\\A"))[0]); input_pool.insert(sigmap(x->getPort("\\A"))[0]);
input_pool.insert(sigmap(x->getPort("\\B"))[0]); input_pool.insert(sigmap(x->getPort("\\B"))[0]);
input_pool_intermed.insert(sigmap(x->getPort("\\Y"))[0]); input_pool_intermed.insert(sigmap(x->getPort("\\Y"))[0]);
} }
SigSpec input; SigSpec input;
for (auto b : input_pool) for (auto b : input_pool)
if (input_pool_intermed.count(b) == 0) if (input_pool_intermed.count(b) == 0)
input.append_bit(b); input.append_bit(b);
SigBit output = sigmap(head_cell->getPort("\\Y")[0]); SigBit output = sigmap(head_cell->getPort("\\Y")[0]);
auto new_reduce_cell = module->addCell(NEW_ID, auto new_reduce_cell = module->addCell(NEW_ID,
gt == GateType::And ? "$reduce_and" : gt == GateType::And ? "$reduce_and" :
gt == GateType::Or ? "$reduce_or" : gt == GateType::Or ? "$reduce_or" :
gt == GateType::Xor ? "$reduce_xor" : ""); gt == GateType::Xor ? "$reduce_xor" : "");
new_reduce_cell->setParam("\\A_SIGNED", 0); new_reduce_cell->setParam("\\A_SIGNED", 0);
new_reduce_cell->setParam("\\A_WIDTH", input.size()); new_reduce_cell->setParam("\\A_WIDTH", input.size());
new_reduce_cell->setParam("\\Y_WIDTH", 1); new_reduce_cell->setParam("\\Y_WIDTH", 1);
new_reduce_cell->setPort("\\A", input); new_reduce_cell->setPort("\\A", input);
new_reduce_cell->setPort("\\Y", output); new_reduce_cell->setPort("\\Y", output);
for (auto x : cur_supercell) for (auto x : cur_supercell)
consumed_cells.insert(x); consumed_cells.insert(x);
} }
} }
// Remove every cell that we've used up // Remove every cell that we've used up
for (auto cell : consumed_cells) for (auto cell : consumed_cells)
module->remove(cell); module->remove(cell);
} }
} }
} RecoverReduceCorePass; } RecoverReduceCorePass;
PRIVATE_NAMESPACE_END PRIVATE_NAMESPACE_END