mirror of https://github.com/YosysHQ/yosys.git
Fixed incorrect port name in cells_map.v
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c04a3d2763
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7498ff8041
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@ -5,7 +5,7 @@ module GP_DFFS(input D, CLK, nSET, output reg Q);
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.SRMODE(1'b1),
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.SRMODE(1'b1),
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) _TECHMAP_REPLACE_ (
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) _TECHMAP_REPLACE_ (
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.D(D),
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.D(D),
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.CLK(C),
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.CLK(CLK),
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.nSR(nSET),
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.nSR(nSET),
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.Q(Q)
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.Q(Q)
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);
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);
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@ -18,7 +18,7 @@ module GP_DFFR(input D, CLK, nRST, output reg Q);
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.SRMODE(1'b0),
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.SRMODE(1'b0),
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) _TECHMAP_REPLACE_ (
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) _TECHMAP_REPLACE_ (
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.D(D),
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.D(D),
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.CLK(C),
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.CLK(CLK),
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.nSR(nRST),
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.nSR(nRST),
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.Q(Q)
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.Q(Q)
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);
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);
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