mirror of https://github.com/YosysHQ/yosys.git
Improve opt_rmdff support for $dlatch cells
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parent
18ea65ef04
commit
7481ba4750
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@ -41,9 +41,27 @@ void remove_init_attr(SigSpec sig)
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bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
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bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
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{
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{
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SigSpec sig_e = dlatch->getPort("\\EN");
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SigSpec sig_e;
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State on_state, off_state;
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if (sig_e == State::S0)
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if (dlatch->type == "$dlatch") {
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sig_e = assign_map(dlatch->getPort("\\EN"));
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on_state = dlatch->getParam("\\EN_POLARITY").as_bool() ? State::S1 : State::S0;
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off_state = dlatch->getParam("\\EN_POLARITY").as_bool() ? State::S0 : State::S1;
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} else
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if (dlatch->type == "$_DLATCH_P_") {
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sig_e = assign_map(dlatch->getPort("\\E"));
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on_state = State::S1;
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off_state = State::S0;
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} else
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if (dlatch->type == "$_DLATCH_N_") {
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sig_e = assign_map(dlatch->getPort("\\E"));
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on_state = State::S0;
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off_state = State::S1;
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} else
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log_abort();
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if (sig_e == off_state)
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{
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{
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RTLIL::Const val_init;
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RTLIL::Const val_init;
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for (auto bit : dff_init_map(dlatch->getPort("\\Q")))
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for (auto bit : dff_init_map(dlatch->getPort("\\Q")))
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@ -52,7 +70,7 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
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goto delete_dlatch;
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goto delete_dlatch;
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}
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}
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if (sig_e == State::S1)
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if (sig_e == on_state)
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{
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{
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mod->connect(dlatch->getPort("\\Q"), dlatch->getPort("\\D"));
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mod->connect(dlatch->getPort("\\Q"), dlatch->getPort("\\D"));
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goto delete_dlatch;
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goto delete_dlatch;
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@ -268,7 +286,7 @@ struct OptRmdffPass : public Pass {
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"$ff", "$dff", "$adff"))
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"$ff", "$dff", "$adff"))
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dff_list.push_back(cell->name);
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dff_list.push_back(cell->name);
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if (cell->type == "$dlatch")
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if (cell->type.in("$dlatch", "$_DLATCH_P_", "$_DLATCH_N_"))
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dlatch_list.push_back(cell->name);
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dlatch_list.push_back(cell->name);
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}
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}
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