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Remove muxY and ffY for now

This commit is contained in:
Eddie Hung 2019-08-08 16:33:37 -07:00
parent 1f722b3500
commit 747690a6df
2 changed files with 33 additions and 35 deletions
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10
passes/pmgen/xilinx_dsp.cc
View File

@ -38,7 +38,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
log("ffB: %s\n", log_id(st.ffB, "--")); log("ffB: %s\n", log_id(st.ffB, "--"));
log("dsp: %s\n", log_id(st.dsp, "--")); log("dsp: %s\n", log_id(st.dsp, "--"));
log("ffP: %s\n", log_id(st.ffP, "--")); log("ffP: %s\n", log_id(st.ffP, "--"));
log("muxP: %s\n", log_id(st.muxP, "--")); //log("muxP: %s\n", log_id(st.muxP, "--"));
log("sigPused: %s\n", log_signal(st.sigPused)); log("sigPused: %s\n", log_signal(st.sigPused));
log_module(pm.module); log_module(pm.module);
#endif #endif
@ -81,9 +81,9 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
if (st.ffP) { if (st.ffP) {
SigSpec P = cell->getPort("\\P"); SigSpec P = cell->getPort("\\P");
SigSpec D; SigSpec D;
if (st.muxP) //if (st.muxP)
D = st.muxP->getPort("\\B"); // D = st.muxP->getPort("\\B");
else //else
D = st.ffP->getPort("\\D"); D = st.ffP->getPort("\\D");
SigSpec Q = st.ffP->getPort("\\Q"); SigSpec Q = st.ffP->getPort("\\Q");
P.replace(pm.sigmap(D), Q); P.replace(pm.sigmap(D), Q);
@ -107,7 +107,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
log(" ffB:%s", log_id(st.ffB)); log(" ffB:%s", log_id(st.ffB));
if (st.ffP) if (st.ffP)
log(" ffY:%s", log_id(st.ffP)); log(" ffP:%s", log_id(st.ffP));
log("\n"); log("\n");
} }

58
passes/pmgen/xilinx_dsp.pmg
View File

@ -47,11 +47,9 @@ endcode
// (as opposed to being a dummy) // (as opposed to being a dummy)
code sigPused code sigPused
SigSpec P = port(dsp, \P); SigSpec P = port(dsp, \P);
int i; for (int i = 0; i < GetSize(P); i++)
for (i = GetSize(P); i > 0; i--) if (P[i].wire && nusers(P[i]) > 1)
if (nusers(P[i-1]) > 1) sigPused.append(P[i]);
break;
sigPused = P.extract(0, i).remove_const();
endcode endcode
match ffP match ffP
@ -66,33 +64,33 @@ match ffP
optional optional
endmatch endmatch
// $mux cell left behind by dff2dffe //// $mux cell left behind by dff2dffe
// would prefer not to run 'opt_expr -mux_undef' //// would prefer not to run 'opt_expr -mux_undef'
// since that would lose information helpful for //// since that would lose information helpful for
// efficient wide-mux inference //// efficient wide-mux inference
match muxP //match muxP
if !sigPused.empty() && !ffP // if !sigPused.empty() && !ffP
select muxP->type.in($mux) // select muxP->type.in($mux)
select nusers(port(muxP, \B)) == 2 // select nusers(port(muxP, \B)) == 2
select port(muxP, \A).is_fully_undef() // select port(muxP, \A).is_fully_undef()
filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused) // filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused)
filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set()) // filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set())
optional // optional
endmatch //endmatch
//
match ffY //match ffY
if muxP // if muxP
select ffY->type.in($dff, $dffe) // select ffY->type.in($dff, $dffe)
select nusers(port(ffY, \D)) == 2 // select nusers(port(ffY, \D)) == 2
// DSP48E1 does not support clock inversion // // DSP48E1 does not support clock inversion
select param(ffY, \CLK_POLARITY).as_bool() // select param(ffY, \CLK_POLARITY).as_bool()
filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused) // filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused)
filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set()) // filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set())
endmatch //endmatch
code ffP clock code ffP clock
if (ffY) // if (ffY)
ffP = ffY; // ffP = ffY;
if (ffP) { if (ffP) {
SigBit c = port(ffP, \CLK).as_bit(); SigBit c = port(ffP, \CLK).as_bit();