diff --git a/docs/source/code_examples/example_synth/Makefile b/docs/source/code_examples/example_synth/Makefile
deleted file mode 100644
index 4446c2099..000000000
--- a/docs/source/code_examples/example_synth/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-PROGRAM_PREFIX :=
-
-YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
-
-DOTS = control_hier.dot control_proc.dot
-DOTS += example_hier.dot
-
-dots: $(DOTS) example.out
-
-$(DOTS) example.out: example.v example.ys
-	$(YOSYS) example.ys -l example.out -Q
-
-.PHONY: clean
-clean:
-	rm -f *.dot
diff --git a/docs/source/code_examples/example_synth/example.out b/docs/source/code_examples/example_synth/example.out
deleted file mode 100644
index f2c4bfafa..000000000
--- a/docs/source/code_examples/example_synth/example.out
+++ /dev/null
@@ -1,147 +0,0 @@
-
--- Executing script file `example.ys' --
-echo on
-
-yosys> read_verilog -defer example.v
-
-1. Executing Verilog-2005 frontend: example.v
-Parsing Verilog input from `example.v' to AST representation.
-Storing AST representation for module `$abstract\example'.
-Storing AST representation for module `$abstract\control'.
-Storing AST representation for module `$abstract\data'.
-Successfully finished Verilog frontend.
-
-yosys> hierarchy -top control
-
-2. Executing HIERARCHY pass (managing design hierarchy).
-
-3. Executing AST frontend in derive mode using pre-parsed AST for module `\control'.
-Generating RTLIL representation for module `\control'.
-
-3.1. Analyzing design hierarchy..
-Top module:  \control
-
-3.2. Analyzing design hierarchy..
-Top module:  \control
-Removing unused module `$abstract\data'.
-Removing unused module `$abstract\control'.
-Removing unused module `$abstract\example'.
-Removed 3 unused modules.
-
-yosys> show -notitle -format dot -prefix control_hier
-
-4. Generating Graphviz representation of design.
-Writing dot description to `control_hier.dot'.
-Dumping module control to page 1.
-
-yosys> proc
-
-5. Executing PROC pass (convert processes to netlists).
-
-yosys> proc_clean
-
-5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
-Cleaned up 0 empty switches.
-
-yosys> proc_rmdead
-
-5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
-Marked 1 switch rules as full_case in process $proc$example.v:43$1 in module control.
-Removed a total of 0 dead cases.
-
-yosys> proc_prune
-
-5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
-Removed 1 redundant assignment.
-Promoted 0 assignments to connections.
-
-yosys> proc_init
-
-5.4. Executing PROC_INIT pass (extract init attributes).
-
-yosys> proc_arst
-
-5.5. Executing PROC_ARST pass (detect async resets in processes).
-
-yosys> proc_rom
-
-5.6. Executing PROC_ROM pass (convert switches to ROMs).
-Converted 0 switches.
-<suppressed ~2 debug messages>
-
-yosys> proc_mux
-
-5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
-Creating decoders for process `\control.$proc$example.v:43$1'.
-     1/2: $0\addr[7:0]
-     2/2: $0\state[1:0]
-
-yosys> proc_dlatch
-
-5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
-
-yosys> proc_dff
-
-5.9. Executing PROC_DFF pass (convert process syncs to FFs).
-Creating register for signal `\control.\state' using process `\control.$proc$example.v:43$1'.
-  created $dff cell `$procdff$12' with positive edge clock.
-Creating register for signal `\control.\addr' using process `\control.$proc$example.v:43$1'.
-  created $dff cell `$procdff$13' with positive edge clock.
-
-yosys> proc_memwr
-
-5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
-
-yosys> proc_clean
-
-5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
-Found and cleaned up 2 empty switches in `\control.$proc$example.v:43$1'.
-Removing empty process `control.$proc$example.v:43$1'.
-Cleaned up 2 empty switches.
-
-yosys> opt_expr -keepdc
-
-5.12. Executing OPT_EXPR pass (perform const folding).
-Optimizing module control.
-
-yosys> show -notitle -format dot -prefix control_proc
-
-6. Generating Graphviz representation of design.
-Writing dot description to `control_proc.dot'.
-Dumping module control to page 1.
-
-yosys> design -reset
-
-yosys> read_verilog example.v
-
-7. Executing Verilog-2005 frontend: example.v
-Parsing Verilog input from `example.v' to AST representation.
-Generating RTLIL representation for module `\example'.
-Generating RTLIL representation for module `\control'.
-Generating RTLIL representation for module `\data'.
-Successfully finished Verilog frontend.
-
-yosys> hierarchy -check -top example
-
-8. Executing HIERARCHY pass (managing design hierarchy).
-
-8.1. Analyzing design hierarchy..
-Top module:  \example
-Used module:     \data
-Used module:     \control
-
-8.2. Analyzing design hierarchy..
-Top module:  \example
-Used module:     \data
-Used module:     \control
-Removed 0 unused modules.
-
-yosys> show -notitle -format dot -prefix example_hier example
-
-9. Generating Graphviz representation of design.
-Writing dot description to `example_hier.dot'.
-Dumping module example to page 1.
-
-End of script. Logfile hash: b45465606c, CPU: user 0.01s system 0.00s, MEM: 11.86 MB peak
-Yosys 0.35+39 (git sha1 0cd4a10c8, clang 10.0.0-4ubuntu1 -fPIC -Os)
-Time spent: 37% 4x read_verilog (0 sec), 23% 3x show (0 sec), ...
diff --git a/docs/source/code_examples/example_synth/example.v b/docs/source/code_examples/example_synth/example.v
deleted file mode 100644
index f0fc5cdb5..000000000
--- a/docs/source/code_examples/example_synth/example.v
+++ /dev/null
@@ -1,76 +0,0 @@
-module example (
-	input clk,
-	input rst,
-	input inc,
-	input [7:0] a,
-	input [7:0] b,
-	output [15:0] c
-);
-
-wire [1:0] state;
-wire [7:0] addr;
-
-control ctrl (
-	.clk(clk),
-	.rst(rst),
-	.inc(inc),
-	.addr_o(addr),
-	.state_o(state)
-);
-
-data dat (
-	.clk(clk),
-	.addr_i(addr),
-	.state_i(state),
-	.a(a),
-	.b(b),
-	.c(c)
-);
-
-endmodule
-
-module control (
-	input clk,
-	input rst,
-	input inc,
-	output [7:0] addr_o,
-	output [1:0] state_o
-);
-
-reg [1:0] state;
-reg [7:0] addr;
-
-always @(posedge clk) begin
-	if (rst) begin
-		state <= 2'b00;
-		addr <= 0;
-	end else begin
-		if (inc) state <= state + 1'b1;
-		addr <= addr + 1'b1;
-	end
-end
-
-endmodule //control
-
-module data (
-	input clk,
-	input [7:0] addr_i,
-	input [1:0] state_i,
-	input [7:0] a,
-	input [7:0] b,
-	output reg [15:0] c
-);
-
-reg [15:0] mem[255:0];
-
-always @(posedge clk) begin
-	case (state_i)
-		2'b00: mem[addr_i] <= a*b;
-		2'b01: mem[addr_i] <= a+b;
-		2'b10: mem[addr_i] <= a-b;
-		2'b11: mem[addr_i] <= addr_i;
-	endcase
-	c <= mem[addr_i];
-end
-
-endmodule //data
diff --git a/docs/source/code_examples/example_synth/example.ys b/docs/source/code_examples/example_synth/example.ys
deleted file mode 100644
index b8745dac5..000000000
--- a/docs/source/code_examples/example_synth/example.ys
+++ /dev/null
@@ -1,17 +0,0 @@
-# turn command echoes on to use the log output as a console session
-echo on
-
-# ========================================================
-read_verilog -defer example.v
-hierarchy -top control
-show -notitle -format dot -prefix control_hier
-
-# ========================================================
-proc
-show -notitle -format dot -prefix control_proc
-
-# ========================================================
-design -reset
-read_verilog example.v
-hierarchy -check -top example
-show -notitle -format dot -prefix example_hier example
diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile
new file mode 100644
index 000000000..e0287eab4
--- /dev/null
+++ b/docs/source/code_examples/fifo/Makefile
@@ -0,0 +1,16 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+DOTS = addr_gen_hier.dot addr_gen_proc.dot
+DOTS += rdata_proc.dot rdata_flat.dot
+DOTS += fifo_flat.dot fifo_synth.dot
+
+dots: $(DOTS) fifo.out
+
+$(DOTS) fifo.out: fifo.v fifo.ys
+	$(YOSYS) fifo.ys -l fifo.out -Q
+
+.PHONY: clean
+clean:
+	rm -f *.dot
diff --git a/docs/source/code_examples/fifo/fifo.out b/docs/source/code_examples/fifo/fifo.out
new file mode 100644
index 000000000..5a4215e5c
--- /dev/null
+++ b/docs/source/code_examples/fifo/fifo.out
@@ -0,0 +1,2331 @@
+
+-- Executing script file `fifo.ys' --
+$ yosys fifo.v
+
+-- Parsing `fifo.v' using frontend ` -vlog2k' --
+
+1. Executing Verilog-2005 frontend: fifo.v
+Parsing Verilog input from `fifo.v' to AST representation.
+Storing AST representation for module `$abstract\addr_gen'.
+Storing AST representation for module `$abstract\fifo'.
+Successfully finished Verilog frontend.
+echo on
+
+yosys> hierarchy -top addr_gen
+
+2. Executing HIERARCHY pass (managing design hierarchy).
+
+3. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
+Generating RTLIL representation for module `\addr_gen'.
+
+3.1. Analyzing design hierarchy..
+Top module:  \addr_gen
+
+3.2. Analyzing design hierarchy..
+Top module:  \addr_gen
+Removing unused module `$abstract\fifo'.
+Removing unused module `$abstract\addr_gen'.
+Removed 2 unused modules.
+
+yosys> show -notitle -format dot -prefix addr_gen_hier
+
+4. Generating Graphviz representation of design.
+Writing dot description to `addr_gen_hier.dot'.
+Dumping module addr_gen to page 1.
+
+yosys> proc
+
+5. Executing PROC pass (convert processes to netlists).
+
+yosys> proc_clean
+
+5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+yosys> proc_rmdead
+
+5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Marked 2 switch rules as full_case in process $proc$fifo.v:13$1 in module addr_gen.
+Removed a total of 0 dead cases.
+
+yosys> proc_prune
+
+5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 0 redundant assignments.
+Promoted 1 assignment to connection.
+
+yosys> proc_init
+
+5.4. Executing PROC_INIT pass (extract init attributes).
+Found init rule in `\addr_gen.$proc$fifo.v:0$4'.
+  Set init value: \addr = 8'00000000
+
+yosys> proc_arst
+
+5.5. Executing PROC_ARST pass (detect async resets in processes).
+Found async reset \rst in `\addr_gen.$proc$fifo.v:13$1'.
+
+yosys> proc_rom
+
+5.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 0 switches.
+<suppressed ~2 debug messages>
+
+yosys> proc_mux
+
+5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `\addr_gen.$proc$fifo.v:0$4'.
+Creating decoders for process `\addr_gen.$proc$fifo.v:13$1'.
+     1/1: $0\addr[7:0]
+
+yosys> proc_dlatch
+
+5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+
+yosys> proc_dff
+
+5.9. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `\addr_gen.\addr' using process `\addr_gen.$proc$fifo.v:13$1'.
+  created $adff cell `$procdff$10' with positive edge clock and positive level reset.
+
+yosys> proc_memwr
+
+5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+yosys> proc_clean
+
+5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Removing empty process `addr_gen.$proc$fifo.v:0$4'.
+Found and cleaned up 2 empty switches in `\addr_gen.$proc$fifo.v:13$1'.
+Removing empty process `addr_gen.$proc$fifo.v:13$1'.
+Cleaned up 2 empty switches.
+
+yosys> opt_expr -keepdc
+
+5.12. Executing OPT_EXPR pass (perform const folding).
+Optimizing module addr_gen.
+
+yosys> show -notitle -format dot -prefix addr_gen_proc
+
+6. Generating Graphviz representation of design.
+Writing dot description to `addr_gen_proc.dot'.
+Dumping module addr_gen to page 1.
+
+yosys> design -reset
+
+yosys> read_verilog fifo.v
+
+7. Executing Verilog-2005 frontend: fifo.v
+Parsing Verilog input from `fifo.v' to AST representation.
+Generating RTLIL representation for module `\addr_gen'.
+Generating RTLIL representation for module `\fifo'.
+Successfully finished Verilog frontend.
+
+yosys> hierarchy -check -top fifo
+
+8. Executing HIERARCHY pass (managing design hierarchy).
+
+8.1. Analyzing design hierarchy..
+Top module:  \fifo
+Used module:     \addr_gen
+Parameter \MAX_DATA = 256
+
+8.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
+Parameter \MAX_DATA = 256
+Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
+Parameter \MAX_DATA = 256
+Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
+
+8.3. Analyzing design hierarchy..
+Top module:  \fifo
+Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
+
+8.4. Analyzing design hierarchy..
+Top module:  \fifo
+Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
+Removing unused module `\addr_gen'.
+Removed 1 unused modules.
+
+yosys> proc
+
+9. Executing PROC pass (convert processes to netlists).
+
+yosys> proc_clean
+
+9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+yosys> proc_rmdead
+
+9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Marked 2 switch rules as full_case in process $proc$fifo.v:64$24 in module fifo.
+Marked 1 switch rules as full_case in process $proc$fifo.v:38$16 in module fifo.
+Marked 2 switch rules as full_case in process $proc$fifo.v:13$32 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
+Removed a total of 0 dead cases.
+
+yosys> proc_prune
+
+9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 0 redundant assignments.
+Promoted 6 assignments to connections.
+
+yosys> proc_init
+
+9.4. Executing PROC_INIT pass (extract init attributes).
+Found init rule in `\fifo.$proc$fifo.v:0$31'.
+  Set init value: \count = 9'000000000
+Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'.
+  Set init value: \addr = 8'00000000
+
+yosys> proc_arst
+
+9.5. Executing PROC_ARST pass (detect async resets in processes).
+Found async reset \rst in `\fifo.$proc$fifo.v:64$24'.
+Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$32'.
+
+yosys> proc_rom
+
+9.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 0 switches.
+<suppressed ~5 debug messages>
+
+yosys> proc_mux
+
+9.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `\fifo.$proc$fifo.v:0$31'.
+Creating decoders for process `\fifo.$proc$fifo.v:64$24'.
+     1/1: $0\count[8:0]
+Creating decoders for process `\fifo.$proc$fifo.v:38$16'.
+     1/3: $1$memwr$\data$fifo.v:40$15_EN[7:0]$22
+     2/3: $1$memwr$\data$fifo.v:40$15_DATA[7:0]$21
+     3/3: $1$memwr$\data$fifo.v:40$15_ADDR[7:0]$20
+Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'.
+Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$32'.
+     1/1: $0\addr[7:0]
+
+yosys> proc_dlatch
+
+9.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+
+yosys> proc_dff
+
+9.9. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:64$24'.
+  created $adff cell `$procdff$55' with positive edge clock and positive level reset.
+Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:38$16'.
+  created $dff cell `$procdff$56' with positive edge clock.
+Creating register for signal `\fifo.$memwr$\data$fifo.v:40$15_ADDR' using process `\fifo.$proc$fifo.v:38$16'.
+  created $dff cell `$procdff$57' with positive edge clock.
+Creating register for signal `\fifo.$memwr$\data$fifo.v:40$15_DATA' using process `\fifo.$proc$fifo.v:38$16'.
+  created $dff cell `$procdff$58' with positive edge clock.
+Creating register for signal `\fifo.$memwr$\data$fifo.v:40$15_EN' using process `\fifo.$proc$fifo.v:38$16'.
+  created $dff cell `$procdff$59' with positive edge clock.
+Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$32'.
+  created $adff cell `$procdff$60' with positive edge clock and positive level reset.
+
+yosys> proc_memwr
+
+9.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+yosys> proc_clean
+
+9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Removing empty process `fifo.$proc$fifo.v:0$31'.
+Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:64$24'.
+Removing empty process `fifo.$proc$fifo.v:64$24'.
+Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:38$16'.
+Removing empty process `fifo.$proc$fifo.v:38$16'.
+Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'.
+Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$32'.
+Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$32'.
+Cleaned up 5 empty switches.
+
+yosys> opt_expr -keepdc
+
+9.12. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
+
+yosys> show -notitle -format dot -prefix rdata_proc o:rdata %ci*
+
+10. Generating Graphviz representation of design.
+Writing dot description to `rdata_proc.dot'.
+Dumping selected parts of module fifo to page 1.
+
+yosys> flatten
+
+11. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
+<suppressed ~2 debug messages>
+
+yosys> show -notitle -format dot -prefix rdata_flat o:rdata %ci*
+
+12. Generating Graphviz representation of design.
+Writing dot description to `rdata_flat.dot'.
+Dumping selected parts of module fifo to page 1.
+
+yosys> opt_clean
+
+13. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 3 unused cells and 25 unused wires.
+<suppressed ~4 debug messages>
+
+yosys> show -notitle -format dot -prefix fifo_flat
+
+14. Generating Graphviz representation of design.
+Writing dot description to `fifo_flat.dot'.
+Dumping module fifo to page 1.
+
+yosys> design -reset
+
+yosys> read_verilog fifo.v
+
+15. Executing Verilog-2005 frontend: fifo.v
+Parsing Verilog input from `fifo.v' to AST representation.
+Generating RTLIL representation for module `\addr_gen'.
+Generating RTLIL representation for module `\fifo'.
+Successfully finished Verilog frontend.
+
+yosys> synth_ice40 -dsp -top fifo
+
+16. Executing SYNTH_ICE40 pass.
+
+yosys> read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v
+
+16.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/cells_sim.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/cells_sim.v' to AST representation.
+Generating RTLIL representation for module `\SB_IO'.
+Generating RTLIL representation for module `\SB_GB_IO'.
+Generating RTLIL representation for module `\SB_GB'.
+Generating RTLIL representation for module `\SB_LUT4'.
+Generating RTLIL representation for module `\SB_CARRY'.
+Generating RTLIL representation for module `\SB_DFF'.
+Generating RTLIL representation for module `\SB_DFFE'.
+Generating RTLIL representation for module `\SB_DFFSR'.
+Generating RTLIL representation for module `\SB_DFFR'.
+Generating RTLIL representation for module `\SB_DFFSS'.
+Generating RTLIL representation for module `\SB_DFFS'.
+Generating RTLIL representation for module `\SB_DFFESR'.
+Generating RTLIL representation for module `\SB_DFFER'.
+Generating RTLIL representation for module `\SB_DFFESS'.
+Generating RTLIL representation for module `\SB_DFFES'.
+Generating RTLIL representation for module `\SB_DFFN'.
+Generating RTLIL representation for module `\SB_DFFNE'.
+Generating RTLIL representation for module `\SB_DFFNSR'.
+Generating RTLIL representation for module `\SB_DFFNR'.
+Generating RTLIL representation for module `\SB_DFFNSS'.
+Generating RTLIL representation for module `\SB_DFFNS'.
+Generating RTLIL representation for module `\SB_DFFNESR'.
+Generating RTLIL representation for module `\SB_DFFNER'.
+Generating RTLIL representation for module `\SB_DFFNESS'.
+Generating RTLIL representation for module `\SB_DFFNES'.
+Generating RTLIL representation for module `\SB_RAM40_4K'.
+Generating RTLIL representation for module `\SB_RAM40_4KNR'.
+Generating RTLIL representation for module `\SB_RAM40_4KNW'.
+Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
+Generating RTLIL representation for module `\ICESTORM_LC'.
+Generating RTLIL representation for module `\SB_PLL40_CORE'.
+Generating RTLIL representation for module `\SB_PLL40_PAD'.
+Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
+Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
+Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
+Generating RTLIL representation for module `\SB_WARMBOOT'.
+Generating RTLIL representation for module `\SB_SPRAM256KA'.
+Generating RTLIL representation for module `\SB_HFOSC'.
+Generating RTLIL representation for module `\SB_LFOSC'.
+Generating RTLIL representation for module `\SB_RGBA_DRV'.
+Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
+Generating RTLIL representation for module `\SB_RGB_DRV'.
+Generating RTLIL representation for module `\SB_I2C'.
+Generating RTLIL representation for module `\SB_SPI'.
+Generating RTLIL representation for module `\SB_LEDDA_IP'.
+Generating RTLIL representation for module `\SB_FILTER_50NS'.
+Generating RTLIL representation for module `\SB_IO_I3C'.
+Generating RTLIL representation for module `\SB_IO_OD'.
+Generating RTLIL representation for module `\SB_MAC16'.
+Generating RTLIL representation for module `\ICESTORM_RAM'.
+Successfully finished Verilog frontend.
+
+yosys> hierarchy -check -top fifo
+
+16.2. Executing HIERARCHY pass (managing design hierarchy).
+
+16.2.1. Analyzing design hierarchy..
+Top module:  \fifo
+Used module:     \addr_gen
+Parameter \MAX_DATA = 256
+
+16.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
+Parameter \MAX_DATA = 256
+Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
+Parameter \MAX_DATA = 256
+Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
+
+16.2.3. Analyzing design hierarchy..
+Top module:  \fifo
+Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
+
+16.2.4. Analyzing design hierarchy..
+Top module:  \fifo
+Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
+Removing unused module `\addr_gen'.
+Removed 1 unused modules.
+
+yosys> proc
+
+16.3. Executing PROC pass (convert processes to netlists).
+
+yosys> proc_clean
+
+16.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+yosys> proc_rmdead
+
+16.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323 in module SB_DFFNES.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316 in module SB_DFFNESS.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312 in module SB_DFFNER.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305 in module SB_DFFNESR.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302 in module SB_DFFNS.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299 in module SB_DFFNSS.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296 in module SB_DFFNR.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293 in module SB_DFFNSR.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285 in module SB_DFFES.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278 in module SB_DFFESS.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274 in module SB_DFFER.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267 in module SB_DFFESR.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264 in module SB_DFFS.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261 in module SB_DFFSS.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258 in module SB_DFFR.
+Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255 in module SB_DFFSR.
+Marked 2 switch rules as full_case in process $proc$fifo.v:64$75 in module fifo.
+Marked 1 switch rules as full_case in process $proc$fifo.v:38$67 in module fifo.
+Marked 2 switch rules as full_case in process $proc$fifo.v:13$463 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
+Removed a total of 0 dead cases.
+
+yosys> proc_prune
+
+16.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 8 redundant assignments.
+Promoted 28 assignments to connections.
+
+yosys> proc_init
+
+16.3.4. Executing PROC_INIT pass (extract init attributes).
+Found init rule in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$326'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$322'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$315'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$311'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$304'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$301'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$298'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$295'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$290'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$288'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$284'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$277'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$273'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$266'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$263'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$260'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$257'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$254'.
+  Set init value: \Q = 1'0
+Found init rule in `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$252'.
+  Set init value: \Q = 1'0
+Found init rule in `\fifo.$proc$fifo.v:0$82'.
+  Set init value: \count = 9'000000000
+Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$466'.
+  Set init value: \addr = 8'00000000
+
+yosys> proc_arst
+
+16.3.5. Executing PROC_ARST pass (detect async resets in processes).
+Found async reset \S in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'.
+Found async reset \R in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'.
+Found async reset \S in `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'.
+Found async reset \R in `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'.
+Found async reset \S in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'.
+Found async reset \R in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'.
+Found async reset \S in `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'.
+Found async reset \R in `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'.
+Found async reset \rst in `\fifo.$proc$fifo.v:64$75'.
+Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'.
+
+yosys> proc_rom
+
+16.3.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 0 switches.
+<suppressed ~23 debug messages>
+
+yosys> proc_mux
+
+16.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+Creating decoders for process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$326'.
+Creating decoders for process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$322'.
+Creating decoders for process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$315'.
+Creating decoders for process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$311'.
+Creating decoders for process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$304'.
+Creating decoders for process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$301'.
+Creating decoders for process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$298'.
+Creating decoders for process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$295'.
+Creating decoders for process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'.
+Creating decoders for process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$290'.
+Creating decoders for process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$289'.
+Creating decoders for process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$288'.
+Creating decoders for process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$284'.
+Creating decoders for process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$277'.
+Creating decoders for process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$273'.
+Creating decoders for process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$266'.
+Creating decoders for process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$263'.
+Creating decoders for process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$260'.
+Creating decoders for process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$257'.
+Creating decoders for process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$254'.
+Creating decoders for process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'.
+     1/1: $0\Q[0:0]
+Creating decoders for process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$252'.
+Creating decoders for process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$251'.
+Creating decoders for process `\fifo.$proc$fifo.v:0$82'.
+Creating decoders for process `\fifo.$proc$fifo.v:64$75'.
+     1/1: $0\count[8:0]
+Creating decoders for process `\fifo.$proc$fifo.v:38$67'.
+     1/3: $1$memwr$\data$fifo.v:40$66_EN[7:0]$73
+     2/3: $1$memwr$\data$fifo.v:40$66_DATA[7:0]$72
+     3/3: $1$memwr$\data$fifo.v:40$66_ADDR[7:0]$71
+Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$466'.
+Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'.
+     1/1: $0\addr[7:0]
+
+yosys> proc_dlatch
+
+16.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+
+yosys> proc_dff
+
+16.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
+Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'.
+  created $adff cell `$procdff$530' with negative edge clock and positive level reset.
+Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'.
+  created $dff cell `$procdff$531' with negative edge clock.
+Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'.
+  created $adff cell `$procdff$532' with negative edge clock and positive level reset.
+Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'.
+  created $dff cell `$procdff$533' with negative edge clock.
+Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'.
+  created $adff cell `$procdff$534' with negative edge clock and positive level reset.
+Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'.
+  created $dff cell `$procdff$535' with negative edge clock.
+Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'.
+  created $adff cell `$procdff$536' with negative edge clock and positive level reset.
+Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'.
+  created $dff cell `$procdff$537' with negative edge clock.
+Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'.
+  created $dff cell `$procdff$538' with negative edge clock.
+Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$289'.
+  created $dff cell `$procdff$539' with negative edge clock.
+Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'.
+  created $adff cell `$procdff$540' with positive edge clock and positive level reset.
+Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'.
+  created $dff cell `$procdff$541' with positive edge clock.
+Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'.
+  created $adff cell `$procdff$542' with positive edge clock and positive level reset.
+Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'.
+  created $dff cell `$procdff$543' with positive edge clock.
+Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'.
+  created $adff cell `$procdff$544' with positive edge clock and positive level reset.
+Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'.
+  created $dff cell `$procdff$545' with positive edge clock.
+Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'.
+  created $adff cell `$procdff$546' with positive edge clock and positive level reset.
+Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'.
+  created $dff cell `$procdff$547' with positive edge clock.
+Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'.
+  created $dff cell `$procdff$548' with positive edge clock.
+Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$251'.
+  created $dff cell `$procdff$549' with positive edge clock.
+Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:64$75'.
+  created $adff cell `$procdff$550' with positive edge clock and positive level reset.
+Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:38$67'.
+  created $dff cell `$procdff$551' with positive edge clock.
+Creating register for signal `\fifo.$memwr$\data$fifo.v:40$66_ADDR' using process `\fifo.$proc$fifo.v:38$67'.
+  created $dff cell `$procdff$552' with positive edge clock.
+Creating register for signal `\fifo.$memwr$\data$fifo.v:40$66_DATA' using process `\fifo.$proc$fifo.v:38$67'.
+  created $dff cell `$procdff$553' with positive edge clock.
+Creating register for signal `\fifo.$memwr$\data$fifo.v:40$66_EN' using process `\fifo.$proc$fifo.v:38$67'.
+  created $dff cell `$procdff$554' with positive edge clock.
+Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'.
+  created $adff cell `$procdff$555' with positive edge clock and positive level reset.
+
+yosys> proc_memwr
+
+16.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+yosys> proc_clean
+
+16.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Removing empty process `SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$326'.
+Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'.
+Removing empty process `SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'.
+Removing empty process `SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$322'.
+Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'.
+Removing empty process `SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'.
+Removing empty process `SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$315'.
+Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'.
+Removing empty process `SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'.
+Removing empty process `SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$311'.
+Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'.
+Removing empty process `SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'.
+Removing empty process `SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$304'.
+Removing empty process `SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'.
+Removing empty process `SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$301'.
+Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'.
+Removing empty process `SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'.
+Removing empty process `SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$298'.
+Removing empty process `SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'.
+Removing empty process `SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$295'.
+Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'.
+Removing empty process `SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'.
+Removing empty process `SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'.
+Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'.
+Removing empty process `SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'.
+Removing empty process `SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$290'.
+Removing empty process `SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$289'.
+Removing empty process `SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$288'.
+Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'.
+Removing empty process `SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'.
+Removing empty process `SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$284'.
+Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'.
+Removing empty process `SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'.
+Removing empty process `SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$277'.
+Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'.
+Removing empty process `SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'.
+Removing empty process `SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$273'.
+Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'.
+Removing empty process `SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'.
+Removing empty process `SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$266'.
+Removing empty process `SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'.
+Removing empty process `SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$263'.
+Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'.
+Removing empty process `SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'.
+Removing empty process `SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$260'.
+Removing empty process `SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'.
+Removing empty process `SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$257'.
+Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'.
+Removing empty process `SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'.
+Removing empty process `SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$254'.
+Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'.
+Removing empty process `SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'.
+Removing empty process `SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$252'.
+Removing empty process `SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$251'.
+Removing empty process `fifo.$proc$fifo.v:0$82'.
+Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:64$75'.
+Removing empty process `fifo.$proc$fifo.v:64$75'.
+Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:38$67'.
+Removing empty process `fifo.$proc$fifo.v:38$67'.
+Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$466'.
+Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'.
+Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'.
+Cleaned up 23 empty switches.
+
+yosys> opt_expr -keepdc
+
+16.3.12. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
+
+yosys> flatten
+
+16.4. Executing FLATTEN pass (flatten design).
+Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
+<suppressed ~2 debug messages>
+
+yosys> tribuf -logic
+
+16.5. Executing TRIBUF pass.
+
+yosys> deminout
+
+16.6. Executing DEMINOUT pass (demote inout ports to input or output).
+
+yosys> opt_expr
+
+16.7. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_clean
+
+16.8. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 3 unused cells and 25 unused wires.
+<suppressed ~4 debug messages>
+
+yosys> check
+
+16.9. Executing CHECK pass (checking for obvious problems).
+Checking module fifo...
+Found and reported 0 problems.
+
+yosys> opt -nodffe -nosdff
+
+16.10. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr
+
+16.10.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge -nomux
+
+16.10.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_muxtree
+
+16.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~6 debug messages>
+
+yosys> opt_reduce
+
+16.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+    Consolidated identical input bits for $mux cell $procmux$517:
+      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\data$fifo.v:40$66_EN[7:0]$70
+      New ports: A=1'0, B=1'1, Y=$0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0]
+      New connections: $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [7:1] = { $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] }
+  Optimizing cells in module \fifo.
+Performed a total of 1 changes.
+
+yosys> opt_merge
+
+16.10.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff -nodffe -nosdff
+
+16.10.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> opt_expr
+
+16.10.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.10.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+yosys> opt_muxtree
+
+16.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~6 debug messages>
+
+yosys> opt_reduce
+
+16.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.10.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff -nodffe -nosdff
+
+16.10.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> opt_expr
+
+16.10.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.10.16. Finished OPT passes. (There is nothing left to do.)
+
+yosys> fsm
+
+16.11. Executing FSM pass (extract and optimize FSM).
+
+yosys> fsm_detect
+
+16.11.1. Executing FSM_DETECT pass (finding FSMs in design).
+
+yosys> fsm_extract
+
+16.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
+
+yosys> fsm_opt
+
+16.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+yosys> opt_clean
+
+16.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> fsm_opt
+
+16.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
+
+yosys> fsm_recode
+
+16.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
+
+yosys> fsm_info
+
+16.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
+
+yosys> fsm_map
+
+16.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
+
+yosys> opt
+
+16.12. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr
+
+16.12.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge -nomux
+
+16.12.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_muxtree
+
+16.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~6 debug messages>
+
+yosys> opt_reduce
+
+16.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.12.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.12.6. Executing OPT_DFF pass (perform DFF optimizations).
+Adding EN signal on $procdff$550 ($adff) from module fifo (D = $0\count[8:0], Q = \count).
+Adding EN signal on $flatten\fifo_writer.$procdff$555 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$526_Y, Q = \fifo_writer.addr).
+Adding EN signal on $flatten\fifo_reader.$procdff$555 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$526_Y, Q = \fifo_reader.addr).
+
+yosys> opt_clean
+
+16.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 2 unused cells and 2 unused wires.
+<suppressed ~3 debug messages>
+
+yosys> opt_expr
+
+16.12.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+<suppressed ~1 debug messages>
+
+16.12.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+yosys> opt_muxtree
+
+16.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~6 debug messages>
+
+yosys> opt_reduce
+
+16.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.12.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.12.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> opt_expr
+
+16.12.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.12.16. Finished OPT passes. (There is nothing left to do.)
+
+yosys> wreduce
+
+16.13. Executing WREDUCE pass (reducing word size of cells).
+Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:68$78 ($add).
+Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:68$78 ($add).
+Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:70$81 ($sub).
+Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:70$81 ($sub).
+Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:20$465 ($add).
+Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:20$465 ($add).
+Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:20$465 ($add).
+Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:20$465 ($add).
+Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:68$78_Y.
+Removed top 23 bits (of 32) from wire fifo.$sub$fifo.v:70$81_Y.
+
+yosys> peepopt
+
+16.14. Executing PEEPOPT pass (run peephole optimizers).
+
+yosys> opt_clean
+
+16.15. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 0 unused cells and 2 unused wires.
+<suppressed ~1 debug messages>
+
+yosys> share
+
+16.16. Executing SHARE pass (SAT-based resource sharing).
+
+yosys> techmap -map +/cmp2lut.v -D LUT_WIDTH=4
+
+16.17. Executing TECHMAP pass (map to technology primitives).
+
+16.17.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/cmp2lut.v
+Parsing Verilog input from `/home/dawn/yosys/share/cmp2lut.v' to AST representation.
+Generating RTLIL representation for module `\_90_lut_cmp_'.
+Successfully finished Verilog frontend.
+
+16.17.2. Continuing TECHMAP pass.
+No more expansions possible.
+<suppressed ~6 debug messages>
+
+yosys> opt_expr
+
+16.18. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_clean
+
+16.19. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> memory_dff
+
+16.20. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
+Checking read port `\data'[0] in module `\fifo': merging output FF to cell.
+    Write port 0: non-transparent.
+
+yosys> wreduce t:$mul
+
+16.21. Executing WREDUCE pass (reducing word size of cells).
+
+yosys> techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16
+
+16.22. Executing TECHMAP pass (map to technology primitives).
+
+16.22.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/mul2dsp.v
+Parsing Verilog input from `/home/dawn/yosys/share/mul2dsp.v' to AST representation.
+Generating RTLIL representation for module `\_80_mul'.
+Generating RTLIL representation for module `\_90_soft_mul'.
+Successfully finished Verilog frontend.
+
+16.22.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/dsp_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/dsp_map.v' to AST representation.
+Generating RTLIL representation for module `\$__MUL16X16'.
+Successfully finished Verilog frontend.
+
+16.22.3. Continuing TECHMAP pass.
+No more expansions possible.
+<suppressed ~5 debug messages>
+
+yosys> select a:mul2dsp
+
+yosys*> setattr -unset mul2dsp
+
+yosys*> opt_expr -fine
+
+16.23. Executing OPT_EXPR pass (perform const folding).
+
+yosys*> wreduce
+
+16.24. Executing WREDUCE pass (reducing word size of cells).
+
+yosys*> select -clear
+
+yosys> ice40_dsp
+
+16.25. Executing ICE40_DSP pass (map multipliers).
+
+yosys> chtype -set $mul t:$__soft_mul
+
+yosys> alumacc
+
+16.26. Executing ALUMACC pass (create $alu and $macc cells).
+Extracting $alu and $macc cells in module fifo:
+  creating $macc model for $add$fifo.v:68$78 ($add).
+  creating $macc model for $flatten\fifo_reader.$add$fifo.v:20$465 ($add).
+  creating $macc model for $flatten\fifo_writer.$add$fifo.v:20$465 ($add).
+  creating $macc model for $sub$fifo.v:70$81 ($sub).
+  creating $alu model for $macc $sub$fifo.v:70$81.
+  creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:20$465.
+  creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:20$465.
+  creating $alu model for $macc $add$fifo.v:68$78.
+  creating $alu cell for $add$fifo.v:68$78: $auto$alumacc.cc:485:replace_alu$574
+  creating $alu cell for $flatten\fifo_reader.$add$fifo.v:20$465: $auto$alumacc.cc:485:replace_alu$577
+  creating $alu cell for $flatten\fifo_writer.$add$fifo.v:20$465: $auto$alumacc.cc:485:replace_alu$580
+  creating $alu cell for $sub$fifo.v:70$81: $auto$alumacc.cc:485:replace_alu$583
+  created 4 $alu and 0 $macc cells.
+
+yosys> opt
+
+16.27. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr
+
+16.27.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge -nomux
+
+16.27.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_muxtree
+
+16.27.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~6 debug messages>
+
+yosys> opt_reduce
+
+16.27.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.27.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.27.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.27.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 1 unused cells and 9 unused wires.
+<suppressed ~2 debug messages>
+
+yosys> opt_expr
+
+16.27.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.27.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+yosys> opt_muxtree
+
+16.27.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~6 debug messages>
+
+yosys> opt_reduce
+
+16.27.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.27.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.27.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.27.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> opt_expr
+
+16.27.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.27.16. Finished OPT passes. (There is nothing left to do.)
+
+yosys> memory -nomap
+
+16.28. Executing MEMORY pass.
+
+yosys> opt_mem
+
+16.28.1. Executing OPT_MEM pass (optimize memories).
+Performed a total of 0 transformations.
+
+yosys> opt_mem_priority
+
+16.28.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
+Performed a total of 0 transformations.
+
+yosys> opt_mem_feedback
+
+16.28.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
+
+yosys> memory_bmux2rom
+
+16.28.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
+
+yosys> memory_dff
+
+16.28.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
+
+yosys> opt_clean
+
+16.28.6. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> memory_share
+
+16.28.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
+
+yosys> opt_mem_widen
+
+16.28.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
+Performed a total of 0 transformations.
+
+yosys> opt_clean
+
+16.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> memory_collect
+
+16.28.10. Executing MEMORY_COLLECT pass (generating $mem cells).
+
+yosys> opt_clean
+
+16.29. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge
+
+16.30. Executing MEMORY_LIBMAP pass (mapping memories to cells).
+mapping memory fifo.data via $__ICE40_RAM4K_
+<suppressed ~68 debug messages>
+
+yosys> techmap -map +/ice40/brams_map.v -map +/ice40/spram_map.v
+
+16.31. Executing TECHMAP pass (map to technology primitives).
+
+16.31.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/brams_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/brams_map.v' to AST representation.
+Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
+Successfully finished Verilog frontend.
+
+16.31.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/spram_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/spram_map.v' to AST representation.
+Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
+Successfully finished Verilog frontend.
+
+16.31.3. Continuing TECHMAP pass.
+Using template $paramod$13b3947419e62b7bbba1b93c77e4155efbe69a94\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_.
+No more expansions possible.
+<suppressed ~26 debug messages>
+
+yosys> ice40_braminit
+
+16.32. Executing ICE40_BRAMINIT pass.
+
+yosys> opt -fast -mux_undef -undriven -fine
+
+16.33. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr -mux_undef -undriven -fine
+
+16.33.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+<suppressed ~13 debug messages>
+
+yosys> opt_merge
+
+16.33.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.33.3. Executing OPT_DFF pass (perform DFF optimizations).
+Removing always-active EN on $auto$mem.cc:1146:emulate_transparency$593 ($dffe) from module fifo.
+
+yosys> opt_clean
+
+16.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 0 unused cells and 18 unused wires.
+<suppressed ~1 debug messages>
+
+16.33.5. Rerunning OPT passes. (Removed registers in this run.)
+
+yosys> opt_expr -mux_undef -undriven -fine
+
+16.33.6. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge
+
+16.33.7. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.33.8. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.33.9. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+16.33.10. Finished fast OPT passes.
+
+yosys> memory_map
+
+16.34. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
+
+yosys> opt -undriven -fine
+
+16.35. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr -undriven -fine
+
+16.35.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge -nomux
+
+16.35.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_muxtree
+
+16.35.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  Evaluating internal representation of mux trees.
+  Analyzing evaluation results.
+Removed 0 multiplexer ports.
+<suppressed ~4 debug messages>
+
+yosys> opt_reduce -fine
+
+16.35.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.35.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.35.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.35.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> opt_expr -undriven -fine
+
+16.35.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.35.9. Finished OPT passes. (There is nothing left to do.)
+
+yosys> ice40_wrapcarry
+
+16.36. Executing ICE40_WRAPCARRY pass (wrap carries).
+
+yosys> techmap -map +/techmap.v -map +/ice40/arith_map.v
+
+16.37. Executing TECHMAP pass (map to technology primitives).
+
+16.37.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v
+Parsing Verilog input from `/home/dawn/yosys/share/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_demux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+16.37.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/arith_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/arith_map.v' to AST representation.
+Generating RTLIL representation for module `\_80_ice40_alu'.
+Successfully finished Verilog frontend.
+
+16.37.3. Continuing TECHMAP pass.
+Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ice40_alu for cells of type $alu.
+Using extmapper simplemap for cells of type $dff.
+Using extmapper simplemap for cells of type $logic_not.
+Using extmapper simplemap for cells of type $logic_and.
+Using extmapper simplemap for cells of type $mux.
+Using extmapper simplemap for cells of type $eq.
+Using extmapper simplemap for cells of type $and.
+Using extmapper simplemap for cells of type $adffe.
+Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu.
+Using extmapper simplemap for cells of type $reduce_bool.
+Using template $paramod$6f67705c43e5e94c02b6ebb52209ce5aa5ade4c1\_80_ice40_alu for cells of type $alu.
+Using extmapper simplemap for cells of type $xor.
+Using extmapper simplemap for cells of type $not.
+Using extmapper simplemap for cells of type $pos.
+No more expansions possible.
+<suppressed ~175 debug messages>
+
+yosys> opt -fast
+
+16.38. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr
+
+16.38.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+<suppressed ~109 debug messages>
+
+yosys> opt_merge
+
+16.38.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+<suppressed ~81 debug messages>
+Removed a total of 27 cells.
+
+yosys> opt_dff
+
+16.38.3. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.38.4. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 11 unused cells and 83 unused wires.
+<suppressed ~12 debug messages>
+
+16.38.5. Finished fast OPT passes.
+
+yosys> ice40_opt
+
+16.39. Executing ICE40_OPT pass (performing simple optimizations).
+
+16.39.1. Running ICE40 specific optimizations.
+Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$574.slice[0].carry: CO=\count [0]
+Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$577.slice[0].carry: CO=\fifo_reader.addr [0]
+Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$580.slice[0].carry: CO=\fifo_writer.addr [0]
+Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$583.slice[0].carry: CO=\count [0]
+
+yosys> opt_expr -mux_undef -undriven
+
+16.39.2. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge
+
+16.39.3. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.39.4. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+16.39.6. Rerunning OPT passes. (Removed registers in this run.)
+
+16.39.7. Running ICE40 specific optimizations.
+
+yosys> opt_expr -mux_undef -undriven
+
+16.39.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge
+
+16.39.9. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.39.10. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+16.39.12. Finished OPT passes. (There is nothing left to do.)
+
+yosys> dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_DFF_?P?_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFF_?P?_ 0 -cell $_SDFFCE_?P?P_ 0 -cell $_DLATCH_?_ x -mince -1
+
+16.40. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
+
+yosys> techmap -map +/ice40/ff_map.v
+
+16.41. Executing TECHMAP pass (map to technology primitives).
+
+16.41.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/ff_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/ff_map.v' to AST representation.
+Generating RTLIL representation for module `\$_DFF_N_'.
+Generating RTLIL representation for module `\$_DFF_P_'.
+Generating RTLIL representation for module `\$_DFFE_NP_'.
+Generating RTLIL representation for module `\$_DFFE_PP_'.
+Generating RTLIL representation for module `\$_DFF_NP0_'.
+Generating RTLIL representation for module `\$_DFF_NP1_'.
+Generating RTLIL representation for module `\$_DFF_PP0_'.
+Generating RTLIL representation for module `\$_DFF_PP1_'.
+Generating RTLIL representation for module `\$_DFFE_NP0P_'.
+Generating RTLIL representation for module `\$_DFFE_NP1P_'.
+Generating RTLIL representation for module `\$_DFFE_PP0P_'.
+Generating RTLIL representation for module `\$_DFFE_PP1P_'.
+Generating RTLIL representation for module `\$_SDFF_NP0_'.
+Generating RTLIL representation for module `\$_SDFF_NP1_'.
+Generating RTLIL representation for module `\$_SDFF_PP0_'.
+Generating RTLIL representation for module `\$_SDFF_PP1_'.
+Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
+Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
+Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
+Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
+Successfully finished Verilog frontend.
+
+16.41.2. Continuing TECHMAP pass.
+Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
+Using template \$_DFF_P_ for cells of type $_DFF_P_.
+No more expansions possible.
+<suppressed ~73 debug messages>
+
+yosys> opt_expr -mux_undef
+
+16.42. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> simplemap
+
+16.43. Executing SIMPLEMAP pass (map simple cells to gate primitives).
+Mapping fifo.$auto$alumacc.cc:485:replace_alu$577.slice[0].carry ($lut).
+Mapping fifo.$auto$alumacc.cc:485:replace_alu$580.slice[0].carry ($lut).
+Mapping fifo.$auto$alumacc.cc:485:replace_alu$583.slice[0].carry ($lut).
+Mapping fifo.$auto$alumacc.cc:485:replace_alu$574.slice[0].carry ($lut).
+
+yosys> ice40_opt -full
+
+16.44. Executing ICE40_OPT pass (performing simple optimizations).
+
+16.44.1. Running ICE40 specific optimizations.
+
+yosys> opt_expr -mux_undef -undriven -full
+
+16.44.2. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+<suppressed ~71 debug messages>
+
+yosys> opt_merge
+
+16.44.3. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+<suppressed ~12 debug messages>
+Removed a total of 4 cells.
+
+yosys> opt_dff
+
+16.44.4. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.44.5. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 0 unused cells and 270 unused wires.
+<suppressed ~1 debug messages>
+
+16.44.6. Rerunning OPT passes. (Removed registers in this run.)
+
+16.44.7. Running ICE40 specific optimizations.
+
+yosys> opt_expr -mux_undef -undriven -full
+
+16.44.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+<suppressed ~1 debug messages>
+
+yosys> opt_merge
+
+16.44.9. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.44.10. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.44.11. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+16.44.12. Rerunning OPT passes. (Removed registers in this run.)
+
+16.44.13. Running ICE40 specific optimizations.
+
+yosys> opt_expr -mux_undef -undriven -full
+
+16.44.14. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+yosys> opt_merge
+
+16.44.15. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.44.16. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.44.17. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+16.44.18. Finished OPT passes. (There is nothing left to do.)
+
+yosys> techmap -map +/ice40/latches_map.v
+
+16.45. Executing TECHMAP pass (map to technology primitives).
+
+16.45.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/latches_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/latches_map.v' to AST representation.
+Generating RTLIL representation for module `\$_DLATCH_N_'.
+Generating RTLIL representation for module `\$_DLATCH_P_'.
+Successfully finished Verilog frontend.
+
+16.45.2. Continuing TECHMAP pass.
+No more expansions possible.
+<suppressed ~4 debug messages>
+
+yosys> read_verilog -D ICE40_HX -icells -lib -specify +/ice40/abc9_model.v
+
+16.46. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/abc9_model.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/abc9_model.v' to AST representation.
+Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'.
+Successfully finished Verilog frontend.
+
+yosys> abc9 -W 250
+
+16.47. Executing ABC9 pass.
+
+yosys> abc9_ops -check
+
+16.47.1. Executing ABC9_OPS pass (helper functions for ABC9).
+
+yosys> abc9_ops -prep_hier
+
+16.47.2. Executing ABC9_OPS pass (helper functions for ABC9).
+
+yosys> scc -specify -set_attr abc9_scc_id {}
+
+16.47.3. Executing SCC pass (detecting logic loops).
+Found 0 SCCs in module fifo.
+Found 0 SCCs.
+
+yosys> abc9_ops -prep_bypass
+
+16.47.4. Executing ABC9_OPS pass (helper functions for ABC9).
+
+yosys> design -stash $abc9
+
+yosys> design -load $abc9_map
+
+yosys> proc
+
+16.47.5. Executing PROC pass (convert processes to netlists).
+
+yosys> proc_clean
+
+16.47.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+yosys> proc_rmdead
+
+16.47.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
+Removed a total of 0 dead cases.
+
+yosys> proc_prune
+
+16.47.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
+Removed 0 redundant assignments.
+Promoted 0 assignments to connections.
+
+yosys> proc_init
+
+16.47.5.4. Executing PROC_INIT pass (extract init attributes).
+
+yosys> proc_arst
+
+16.47.5.5. Executing PROC_ARST pass (detect async resets in processes).
+
+yosys> proc_rom
+
+16.47.5.6. Executing PROC_ROM pass (convert switches to ROMs).
+Converted 0 switches.
+
+yosys> proc_mux
+
+16.47.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
+
+yosys> proc_dlatch
+
+16.47.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).
+
+yosys> proc_dff
+
+16.47.5.9. Executing PROC_DFF pass (convert process syncs to FFs).
+
+yosys> proc_memwr
+
+16.47.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
+
+yosys> proc_clean
+
+16.47.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
+Cleaned up 0 empty switches.
+
+yosys> opt_expr -keepdc
+
+16.47.5.12. Executing OPT_EXPR pass (perform const folding).
+
+yosys> wbflip
+
+yosys> techmap -wb -map %$abc9 -map +/techmap.v A:abc9_flop
+
+16.47.6. Executing TECHMAP pass (map to technology primitives).
+
+16.47.6.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v
+Parsing Verilog input from `/home/dawn/yosys/share/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_demux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+16.47.6.2. Continuing TECHMAP pass.
+No more expansions possible.
+<suppressed ~128 debug messages>
+
+yosys> opt -nodffe -nosdff
+
+16.47.7. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr
+
+16.47.7.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module SB_DFFER.
+
+yosys> opt_merge -nomux
+
+16.47.7.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\SB_DFFER'.
+Removed a total of 0 cells.
+
+yosys> opt_muxtree
+
+16.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \SB_DFFER..
+  Creating internal representation of mux trees.
+  No muxes found in this module.
+Removed 0 multiplexer ports.
+
+yosys> opt_reduce
+
+16.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \SB_DFFER.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.47.7.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\SB_DFFER'.
+Removed a total of 0 cells.
+
+yosys> opt_dff -nodffe -nosdff
+
+16.47.7.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean
+
+16.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \SB_DFFER..
+
+yosys> opt_expr
+
+16.47.7.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module SB_DFFER.
+
+16.47.7.9. Finished OPT passes. (There is nothing left to do.)
+
+yosys> design -stash $abc9_map
+
+yosys> design -load $abc9
+
+yosys> design -delete $abc9
+
+yosys> techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v a:abc9_scc_id %n
+
+16.47.8. Executing TECHMAP pass (map to technology primitives).
+
+16.47.8.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/abc9_map.v' to AST representation.
+Successfully finished Verilog frontend.
+
+16.47.8.2. Continuing TECHMAP pass.
+Using template SB_DFFER for cells of type SB_DFFER.
+No more expansions possible.
+<suppressed ~28 debug messages>
+
+yosys> design -delete $abc9_map
+
+yosys> read_verilog -icells -lib -specify +/abc9_model.v
+
+16.47.9. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_model.v
+Parsing Verilog input from `/home/dawn/yosys/share/abc9_model.v' to AST representation.
+Generating RTLIL representation for module `$__ABC9_DELAY'.
+Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
+Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
+Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
+Successfully finished Verilog frontend.
+
+yosys> abc9_ops -break_scc -prep_delays -prep_xaiger
+
+16.47.10. Executing ABC9_OPS pass (helper functions for ABC9).
+<suppressed ~86 debug messages>
+
+yosys> abc9_ops -prep_lut 0
+
+16.47.11. Executing ABC9_OPS pass (helper functions for ABC9).
+
+yosys> abc9_ops -prep_box
+
+16.47.12. Executing ABC9_OPS pass (helper functions for ABC9).
+<suppressed ~2 debug messages>
+
+yosys> design -stash $abc9
+
+yosys> design -load $abc9_holes
+
+yosys> techmap -wb -map %$abc9 -map +/techmap.v
+
+16.47.13. Executing TECHMAP pass (map to technology primitives).
+
+16.47.13.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v
+Parsing Verilog input from `/home/dawn/yosys/share/techmap.v' to AST representation.
+Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
+Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
+Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
+Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
+Generating RTLIL representation for module `\_90_simplemap_various'.
+Generating RTLIL representation for module `\_90_simplemap_registers'.
+Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
+Generating RTLIL representation for module `\_90_shift_shiftx'.
+Generating RTLIL representation for module `\_90_fa'.
+Generating RTLIL representation for module `\_90_lcu'.
+Generating RTLIL representation for module `\_90_alu'.
+Generating RTLIL representation for module `\_90_macc'.
+Generating RTLIL representation for module `\_90_alumacc'.
+Generating RTLIL representation for module `\$__div_mod_u'.
+Generating RTLIL representation for module `\$__div_mod_trunc'.
+Generating RTLIL representation for module `\_90_div'.
+Generating RTLIL representation for module `\_90_mod'.
+Generating RTLIL representation for module `\$__div_mod_floor'.
+Generating RTLIL representation for module `\_90_divfloor'.
+Generating RTLIL representation for module `\_90_modfloor'.
+Generating RTLIL representation for module `\_90_pow'.
+Generating RTLIL representation for module `\_90_pmux'.
+Generating RTLIL representation for module `\_90_demux'.
+Generating RTLIL representation for module `\_90_lut'.
+Successfully finished Verilog frontend.
+
+16.47.13.2. Continuing TECHMAP pass.
+Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
+Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4.
+Using template SB_CARRY for cells of type SB_CARRY.
+Using extmapper simplemap for cells of type $mux.
+Using extmapper simplemap for cells of type $logic_and.
+Using extmapper simplemap for cells of type $logic_or.
+No more expansions possible.
+<suppressed ~155 debug messages>
+
+yosys> opt -purge
+
+16.47.14. Executing OPT pass (performing simple optimizations).
+
+yosys> opt_expr
+
+16.47.14.1. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+<suppressed ~4 debug messages>
+
+yosys> opt_merge -nomux
+
+16.47.14.2. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+<suppressed ~29 debug messages>
+Removed a total of 12 cells.
+
+yosys> opt_muxtree
+
+16.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  No muxes found in this module.
+Removed 0 multiplexer ports.
+
+yosys> opt_reduce
+
+16.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.47.14.5. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.47.14.6. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean -purge
+
+16.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+Removed 0 unused cells and 24 unused wires.
+<suppressed ~1 debug messages>
+
+yosys> opt_expr
+
+16.47.14.8. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.47.14.9. Rerunning OPT passes. (Maybe there is more to do..)
+
+yosys> opt_muxtree
+
+16.47.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
+Running muxtree optimizer on module \fifo..
+  Creating internal representation of mux trees.
+  No muxes found in this module.
+Removed 0 multiplexer ports.
+
+yosys> opt_reduce
+
+16.47.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
+  Optimizing cells in module \fifo.
+Performed a total of 0 changes.
+
+yosys> opt_merge
+
+16.47.14.12. Executing OPT_MERGE pass (detect identical cells).
+Finding identical cells in module `\fifo'.
+Removed a total of 0 cells.
+
+yosys> opt_dff
+
+16.47.14.13. Executing OPT_DFF pass (perform DFF optimizations).
+
+yosys> opt_clean -purge
+
+16.47.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
+Finding unused cells or wires in module \fifo..
+
+yosys> opt_expr
+
+16.47.14.15. Executing OPT_EXPR pass (perform const folding).
+Optimizing module fifo.
+
+16.47.14.16. Finished OPT passes. (There is nothing left to do.)
+
+yosys> aigmap
+
+16.47.15. Executing AIGMAP pass (map logic to AIG).
+Module fifo: replaced 7 cells with 43 new cells, skipped 11 cells.
+  replaced 2 cell types:
+       2 $_OR_
+       5 $_MUX_
+  not replaced 3 cell types:
+       8 $specify2
+       1 $_NOT_
+       2 $_AND_
+
+yosys> design -stash $abc9_holes
+
+yosys> design -load $abc9
+
+yosys> design -delete $abc9
+
+yosys> aigmap
+
+16.47.16. Executing AIGMAP pass (map logic to AIG).
+Module fifo: replaced 46 cells with 256 new cells, skipped 230 cells.
+  replaced 3 cell types:
+      22 $_OR_
+       8 $_XOR_
+      16 $_MUX_
+  not replaced 15 cell types:
+      20 $_NOT_
+      19 $_AND_
+      11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011100000
+      26 SB_DFF
+      25 SB_DFFER
+      30 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1
+      11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011
+      25 SB_DFFER_$abc9_byp
+       1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000001100010
+       2 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100001011
+      16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010100001
+       1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010000101
+       1 $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K
+      16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100010010
+      26 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000000010101
+
+yosys*> abc9_ops -write_lut /tmp/yosys-abc-Sf9BQI/input.lut
+
+16.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9).
+
+yosys*> abc9_ops -write_box /tmp/yosys-abc-Sf9BQI/input.box
+
+16.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9).
+
+yosys*> write_xaiger -map /tmp/yosys-abc-Sf9BQI/input.sym /tmp/yosys-abc-Sf9BQI/input.xaig
+
+16.47.16.3. Executing XAIGER backend.
+<suppressed ~78 debug messages>
+Extracted 113 AND gates and 562 wires from module `fifo' to a netlist network with 71 inputs and 127 outputs.
+
+yosys*> abc9_exe -W 250 -cwd /tmp/yosys-abc-Sf9BQI -lut /tmp/yosys-abc-Sf9BQI/input.lut -box /tmp/yosys-abc-Sf9BQI/input.box
+
+16.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).
+
+16.47.16.5. Executing ABC9.
+Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
+ABC: ABC command line: "source <abc-temp-dir>/abc.script".
+ABC: 
+ABC: + read_lut <abc-temp-dir>/input.lut 
+ABC: + read_box <abc-temp-dir>/input.box 
+ABC: + &read <abc-temp-dir>/input.xaig 
+ABC: + &ps 
+ABC: <abc-temp-dir>/input : i/o =     71/    127  and =     113  lev =    6 (0.27)  mem = 0.01 MB  box = 139  bb = 109
+ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 20 carries.
+ABC: + &scorr 
+ABC: Warning: The network is combinational.
+ABC: + &sweep 
+ABC: + &dc2 
+ABC: + &dch -f 
+ABC: + &ps 
+ABC: <abc-temp-dir>/input : i/o =     71/    127  and =     160  lev =    6 (0.12)  mem = 0.01 MB  ch =   20  box = 139  bb = 109
+ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 20 carries.
+ABC: + &if -W 250 -v 
+ABC: K = 4. Memory (bytes): Truth =    0. Cut =   48. Obj =  128. Set =  528. CutMin = no
+ABC: Node =     160.  Ch =    19.  Total mem =    0.11 MB. Peak cut mem =    0.01 MB.
+ABC: P:  Del = 2712.00.  Ar =      28.0.  Edge =       81.  Cut =      569.  T =     0.00 sec
+ABC: P:  Del = 2712.00.  Ar =      27.0.  Edge =       87.  Cut =      564.  T =     0.00 sec
+ABC: P:  Del = 2712.00.  Ar =      26.0.  Edge =       86.  Cut =      565.  T =     0.00 sec
+ABC: F:  Del = 2712.00.  Ar =      26.0.  Edge =       88.  Cut =      554.  T =     0.00 sec
+ABC: A:  Del = 2712.00.  Ar =      26.0.  Edge =       86.  Cut =      537.  T =     0.00 sec
+ABC: A:  Del = 2712.00.  Ar =      26.0.  Edge =       86.  Cut =      545.  T =     0.00 sec
+ABC: Total time =     0.00 sec
+ABC: + &write -n <abc-temp-dir>/output.aig 
+ABC: + &mfs 
+ABC: The network is not changed by "&mfs".
+ABC: + &ps -l 
+ABC: <abc-temp-dir>/input : i/o =     71/    127  and =      91  lev =    6 (0.12)  mem = 0.01 MB  box = 139  bb = 109
+ABC: Mapping (K=4)  :  lut =     26  edge =      86  lev =    3 (0.05)  levB =   10  mem = 0.00 MB
+ABC: LUT = 26 : 2=4 15.4 %  3=10 38.5 %  4=12 46.2 %  Ave = 3.31
+ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 20 carries.
+ABC: + &write -n <abc-temp-dir>/output.aig 
+ABC: + time 
+ABC: elapse: 0.01 seconds, total: 0.01 seconds
+
+yosys*> read_aiger -xaiger -wideports -module_name fifo$abc9 -map /tmp/yosys-abc-Sf9BQI/input.sym /tmp/yosys-abc-Sf9BQI/output.aig
+
+16.47.16.6. Executing AIGER frontend.
+
+yosys> clean
+<suppressed ~408 debug messages>
+Removed 175 unused cells and 883 unused wires.
+
+yosys*> abc9_ops -reintegrate
+
+16.47.16.7. Executing ABC9_OPS pass (helper functions for ABC9).
+ABC RESULTS:              $lut cells:       29
+ABC RESULTS:   $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells:       30
+ABC RESULTS:   \SB_DFFER_$abc9_byp cells:       25
+ABC RESULTS:           input signals:       36
+ABC RESULTS:          output signals:       91
+Removing temp directory.
+
+yosys> techmap -wb -map %$abc9_unmap -map +/abc9_unmap.v
+
+16.47.17. Executing TECHMAP pass (map to technology primitives).
+
+16.47.17.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_unmap.v
+Parsing Verilog input from `/home/dawn/yosys/share/abc9_unmap.v' to AST representation.
+Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
+Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
+Successfully finished Verilog frontend.
+
+16.47.17.2. Continuing TECHMAP pass.
+Using template SB_DFFER_$abc9_byp for cells of type SB_DFFER_$abc9_byp.
+Using template $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K for cells of type $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K.
+Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
+No more expansions possible.
+<suppressed ~64 debug messages>
+
+yosys> design -delete $abc9_unmap
+
+yosys> design -delete $abc9_holes
+
+yosys> delete =*_$abc9_byp
+
+yosys> setattr -mod -unset abc9_box_id
+
+yosys> ice40_wrapcarry -unwrap
+
+16.48. Executing ICE40_WRAPCARRY pass (wrap carries).
+
+yosys> techmap -map +/ice40/ff_map.v
+
+16.49. Executing TECHMAP pass (map to technology primitives).
+
+16.49.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/ff_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/ff_map.v' to AST representation.
+Generating RTLIL representation for module `\$_DFF_N_'.
+Generating RTLIL representation for module `\$_DFF_P_'.
+Generating RTLIL representation for module `\$_DFFE_NP_'.
+Generating RTLIL representation for module `\$_DFFE_PP_'.
+Generating RTLIL representation for module `\$_DFF_NP0_'.
+Generating RTLIL representation for module `\$_DFF_NP1_'.
+Generating RTLIL representation for module `\$_DFF_PP0_'.
+Generating RTLIL representation for module `\$_DFF_PP1_'.
+Generating RTLIL representation for module `\$_DFFE_NP0P_'.
+Generating RTLIL representation for module `\$_DFFE_NP1P_'.
+Generating RTLIL representation for module `\$_DFFE_PP0P_'.
+Generating RTLIL representation for module `\$_DFFE_PP1P_'.
+Generating RTLIL representation for module `\$_SDFF_NP0_'.
+Generating RTLIL representation for module `\$_SDFF_NP1_'.
+Generating RTLIL representation for module `\$_SDFF_PP0_'.
+Generating RTLIL representation for module `\$_SDFF_PP1_'.
+Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
+Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
+Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
+Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
+Successfully finished Verilog frontend.
+
+16.49.2. Continuing TECHMAP pass.
+No more expansions possible.
+<suppressed ~22 debug messages>
+
+yosys> clean
+Removed 7 unused cells and 1055 unused wires.
+
+yosys> opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -dlogic SB_CARRY:CO=3
+
+16.50. Executing OPT_LUT pass (optimize LUTs).
+Discovering LUTs.
+Number of LUTs:       58
+  1-LUT                3
+  2-LUT                8
+  3-LUT               35
+  4-LUT               12
+  with \SB_CARRY    (#0)   25
+  with \SB_CARRY    (#1)   26
+
+Eliminating LUTs.
+Number of LUTs:       58
+  1-LUT                3
+  2-LUT                8
+  3-LUT               35
+  4-LUT               12
+  with \SB_CARRY    (#0)   25
+  with \SB_CARRY    (#1)   26
+
+Combining LUTs.
+Number of LUTs:       58
+  1-LUT                3
+  2-LUT                8
+  3-LUT               35
+  4-LUT               12
+  with \SB_CARRY    (#0)   25
+  with \SB_CARRY    (#1)   26
+
+Eliminated 0 LUTs.
+Combined 0 LUTs.
+<suppressed ~334 debug messages>
+
+yosys> techmap -map +/ice40/cells_map.v
+
+16.51. Executing TECHMAP pass (map to technology primitives).
+
+16.51.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/cells_map.v
+Parsing Verilog input from `/home/dawn/yosys/share/ice40/cells_map.v' to AST representation.
+Generating RTLIL representation for module `\$lut'.
+Successfully finished Verilog frontend.
+
+16.51.2. Continuing TECHMAP pass.
+Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
+Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
+Using template $paramod$e87f431398fe61dc3cef677df705fdf1c11aa0f7\$lut for cells of type $lut.
+Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
+Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
+Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
+Using template $paramod$2b29ccbd5fb8b9c557f92ddec1023c75686f32ae\$lut for cells of type $lut.
+Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
+Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut.
+Using template $paramod$5c7d886f3b88971ac55fed4bca034a87bf180f7d\$lut for cells of type $lut.
+Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
+Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
+Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
+Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001011 for cells of type $lut.
+No more expansions possible.
+<suppressed ~243 debug messages>
+
+yosys> clean
+Removed 0 unused cells and 130 unused wires.
+
+yosys> autoname
+
+16.52. Executing AUTONAME pass.
+Renamed 1254 objects in module fifo (21 iterations).
+<suppressed ~213 debug messages>
+
+yosys> hierarchy -check
+
+16.53. Executing HIERARCHY pass (managing design hierarchy).
+
+16.53.1. Analyzing design hierarchy..
+Top module:  \fifo
+
+16.53.2. Analyzing design hierarchy..
+Top module:  \fifo
+Removed 0 unused modules.
+
+yosys> stat
+
+16.54. Printing statistics.
+
+=== fifo ===
+
+   Number of wires:                 91
+   Number of wire bits:            246
+   Number of public wires:          91
+   Number of public wire bits:     246
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                136
+     SB_CARRY                       26
+     SB_DFF                         26
+     SB_DFFER                       25
+     SB_LUT4                        58
+     SB_RAM40_4K                     1
+
+
+yosys> check -noinit
+
+16.55. Executing CHECK pass (checking for obvious problems).
+Checking module fifo...
+Found and reported 0 problems.
+
+yosys> blackbox =A:whitebox
+
+yosys> show -notitle -format dot -prefix fifo_synth
+
+17. Generating Graphviz representation of design.
+Writing dot description to `fifo_synth.dot'.
+Dumping module fifo to page 1.
+
+yosys> stat
+
+18. Printing statistics.
+
+=== fifo ===
+
+   Number of wires:                 91
+   Number of wire bits:            246
+   Number of public wires:          91
+   Number of public wire bits:     246
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                136
+     SB_CARRY                       26
+     SB_DFF                         26
+     SB_DFFER                       25
+     SB_LUT4                        58
+     SB_RAM40_4K                     1
+
+End of script. Logfile hash: 7fbdf4b991, CPU: user 0.68s system 0.01s, MEM: 29.84 MB peak
+Yosys 0.35+39 (git sha1 0cd4a10c8, clang 10.0.0-4ubuntu1 -fPIC -Os)
+Time spent: 37% 27x read_verilog (0 sec), 33% 12x techmap (0 sec), ...
diff --git a/docs/source/code_examples/fifo/fifo.v b/docs/source/code_examples/fifo/fifo.v
new file mode 100644
index 000000000..e70005765
--- /dev/null
+++ b/docs/source/code_examples/fifo/fifo.v
@@ -0,0 +1,73 @@
+// address generator/counter
+module addr_gen 
+#(  parameter MAX_DATA=256
+) ( input en, clk, rst,
+	output reg [AWIDTH-1:0] addr
+);
+	localparam AWIDTH = $clog2(MAX_DATA);
+
+	initial addr <= 0;
+
+	// async reset
+	// increment address when enabled
+	always @(posedge clk or posedge rst)
+		if (rst)
+			addr <= 0;
+		else if (en) begin
+			if (addr == MAX_DATA-1)
+				addr <= 0;
+			else
+				addr <= addr + 1;
+		end
+endmodule //addr_gen
+
+// Define our top level fifo entity
+module fifo 
+#(  parameter MAX_DATA=256
+) ( input wen, ren, clk, rst,
+	input [7:0] wdata,
+	output reg [7:0] rdata,
+	output reg [AWIDTH:0] count
+);
+	localparam AWIDTH = $clog2(MAX_DATA);
+
+	// fifo storage
+	// sync read before write
+	wire [AWIDTH-1:0] waddr, raddr;
+	reg [7:0] data [MAX_DATA-1:0];
+	always @(posedge clk) begin
+		if (wen)
+			data[waddr] <= wdata;
+		rdata <= data[raddr];
+	end // storage
+
+	// addr_gen for both write and read addresses
+	addr_gen #(.MAX_DATA(MAX_DATA))
+	fifo_writer (
+		.en     (wen),
+		.clk    (clk),
+		.rst    (rst),
+		.addr   (waddr)
+	);
+
+	addr_gen #(.MAX_DATA(MAX_DATA))
+	fifo_reader (
+		.en     (ren),
+		.clk    (clk),
+		.rst    (rst),
+		.addr   (raddr)
+	);
+
+	// status signals
+	initial count <= 0;
+
+	always @(posedge clk or posedge rst) begin
+		if (rst)
+			count <= 0;
+		else if (wen && !ren)
+			count <= count + 1;
+		else if (ren && !wen)
+			count <= count - 1;
+	end
+
+endmodule
diff --git a/docs/source/code_examples/fifo/fifo.ys b/docs/source/code_examples/fifo/fifo.ys
new file mode 100644
index 000000000..d0274e38b
--- /dev/null
+++ b/docs/source/code_examples/fifo/fifo.ys
@@ -0,0 +1,39 @@
+# ========================================================
+# throw in some extra text to match what we expect if we were opening an
+# interactive terminal
+log $ yosys fifo.v
+log 
+log -- Parsing `fifo.v' using frontend ` -vlog2k' --
+read_verilog -defer fifo.v
+
+# turn command echoes on to use the log output as a console session
+echo on
+hierarchy -top addr_gen
+show -notitle -format dot -prefix addr_gen_hier
+
+# ========================================================
+proc
+show -notitle -format dot -prefix addr_gen_proc
+
+# ========================================================
+design -reset
+read_verilog fifo.v
+hierarchy -check -top fifo
+proc
+show -notitle -format dot -prefix rdata_proc o:rdata %ci*
+
+# ========================================================
+
+flatten
+show -notitle -format dot -prefix rdata_flat o:rdata %ci*
+
+# ========================================================
+
+opt_clean
+show -notitle -format dot -prefix fifo_flat
+
+design -reset
+read_verilog fifo.v
+synth_ice40 -dsp -top fifo
+show -notitle -format dot -prefix fifo_synth
+stat
diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst
index bedaa035c..3c43be269 100644
--- a/docs/source/getting_started/example_synth.rst
+++ b/docs/source/getting_started/example_synth.rst
@@ -23,37 +23,29 @@ First, let's quickly look at the design we'll be synthesizing:
 
 .. todo:: reconsider including the whole (~77 line) design like this
 
-.. literalinclude:: /code_examples/example_synth/example.v
+.. literalinclude:: /code_examples/fifo/fifo.v
    :language: Verilog
    :linenos:
-   :caption: ``example.v``
-   :name: example-v
+   :caption: ``fifo.v``
+   :name: fifo-v
 
-.. todo:: example.v description
+.. todo:: fifo.v description
 
 Loading the design
 ~~~~~~~~~~~~~~~~~~
 
 Let's load the design into Yosys.  From the command line, we can call ``yosys
-example.v``.  This will open an interactive Yosys shell session and immediately
-parse the code from ``example.v`` and convert it into an Abstract Syntax Tree
+fifo.v``.  This will open an interactive Yosys shell session and immediately
+parse the code from ``fifo.v`` and convert it into an Abstract Syntax Tree
 (AST).  If you are interested in how this happens, there is more information in
 the document, :doc:`/yosys_internals/flow/verilog_frontend`.  For now, suffice
 it to say that we do this to simplify further processing of the design.  You
 should see something like the following:
 
-.. code:: console
-
-   $ yosys example.v
-
-   -- Parsing `example.v' using frontend ` -vlog2k' --
-
-   1. Executing Verilog-2005 frontend: example.v
-   Parsing Verilog input from `example.v' to AST representation.
-   Storing AST representation for module `$abstract\example'.
-   Storing AST representation for module `$abstract\control'.
-   Storing AST representation for module `$abstract\data'.
-   Successfully finished Verilog frontend.
+.. literalinclude:: /code_examples/fifo/fifo.out
+   :language: console
+   :start-at: $ yosys fifo.v
+   :end-before: echo on
 
 .. seealso:: Advanced usage docs for
    :doc:`/using_yosys/more_scripting/load_design`
@@ -62,10 +54,10 @@ Elaboration
 ~~~~~~~~~~~
 
 Now that we are in the interactive shell, we can call Yosys commands directly.
-Our overall goal is to call :yoscrypt:`synth_ice40 -top example`, but for now we
+Our overall goal is to call :yoscrypt:`synth_ice40 -top fifo`, but for now we
 can run each of the commands individually for a better sense of how each part
 contributes to the flow.  We will also start with just a single module;
-``control``.
+``addr_gen``.
 
 At the bottom of the :cmd:ref:`help` output for
 :cmd:ref:`synth_ice40` is the complete list of commands called by this script.
@@ -86,20 +78,20 @@ design.  PLLs are a common example of this, where we might need to reference
 later.  Since our simple design doesn't use any of these IP blocks, we can safely
 skip this command.
 
-The control module
-^^^^^^^^^^^^^^^^^^
+The addr_gen module
+^^^^^^^^^^^^^^^^^^^
 
 Since we're just getting started, let's instead begin with :yoscrypt:`hierarchy
--top control`.  This command declares that the top level module is ``control``,
+-top addr_gen`.  This command declares that the top level module is ``addr_gen``,
 and everything else can be discarded.
 
-.. literalinclude:: /code_examples/example_synth/example.v
+.. literalinclude:: /code_examples/fifo/fifo.v
    :language: Verilog
-   :start-at: module control
-   :end-at: endmodule //control
+   :start-at: module addr_gen
+   :end-at: endmodule //addr_gen
    :lineno-match:
-   :caption: ``control`` module source
-   :name: control-v
+   :caption: ``addr_gen`` module source
+   :name: addr_gen-v
 
 .. note::
 
@@ -108,26 +100,26 @@ and everything else can be discarded.
 
 .. use doscon for a console-like display that supports the `yosys> [command]` format.
 
-.. literalinclude:: /code_examples/example_synth/example.out
+.. literalinclude:: /code_examples/fifo/fifo.out
    :language: doscon
-   :start-at: yosys> hierarchy -top control
+   :start-at: yosys> hierarchy -top addr_gen
    :end-before: yosys> show
-   :caption: :yoscrypt:`hierarchy -top control` output
+   :caption: :yoscrypt:`hierarchy -top addr_gen` output
 
-Our ``control`` circuit now looks like this:
+Our ``addr_gen`` circuit now looks like this:
 
-.. figure:: /_images/code_examples/example_synth/control_hier.*
+.. figure:: /_images/code_examples/fifo/addr_gen_hier.*
    :class: width-helper
-   :name: control_hier
+   :name: addr_gen_hier
 
-   ``control`` module after :cmd:ref:`hierarchy`
+   ``addr_gen`` module after :cmd:ref:`hierarchy`
 
-Notice that block that says "PROC" in :ref:`control_hier`?  Simple operations
-like ``addr + 1'b1`` can be extracted from our ``always @`` block in
-:ref:`control-v`. This gives us the two ``$add`` cells we see.  But control
-logic (like the ``if .. else``) and memory elements (like the ``addr <= 0``) are
-not so straightforward. To handle these, let us now introduce the next command:
-:doc:`/cmd/proc`.
+Notice that block that says "PROC" in :ref:`addr_gen_hier`?  Simple operations
+like ``addr + 1`` and ``addr == MAX_DATA-1`` can be extracted from our ``always
+@`` block in :ref:`addr_gen-v`. This gives us the ``$add`` and ``$eq`` cells we
+see. But control logic (like the ``if .. else``) and memory elements (like the
+``addr <= 0``) are not so straightforward. To handle these, let us now introduce
+the next command: :doc:`/cmd/proc`.
 
 :cmd:ref:`proc` is a macro command like :cmd:ref:`synth_ice40`.  Rather than
 modifying the design directly, it instead calls a series of other commands.  In
@@ -135,68 +127,81 @@ the case of :cmd:ref:`proc`, these sub-commands work to convert the behavioral
 logic of processes into multiplexers and registers.  Let's see what happens when
 we run it.
 
-.. figure:: /_images/code_examples/example_synth/control_proc.*
+.. figure:: /_images/code_examples/fifo/addr_gen_proc.*
    :class: width-helper
+   :name: addr_gen_proc
 
-   ``control`` module after :cmd:ref:`proc`
+   ``addr_gen`` module after :cmd:ref:`proc`
 
-The ``if`` statements are now modeled with ``$mux`` cells, while the registers
-use ``$dff`` cells.  If we look at the terminal output we can also see all of
-the different ``proc_*`` commands being called.  We will look at each of these
-in more detail in :doc:`/using_yosys/synthesis/proc`.
+The ``if`` statements are now modeled with ``$mux`` cells, while the register
+uses an ``$adff`` cells.  If we look at the terminal output we can also see all
+of the different ``proc_*`` commands being called.  We will look at each of
+these in more detail in :doc:`/using_yosys/synthesis/proc`.
+
+.. todo:: consider a brief glossary for terms like adff
 
 The full example
 ^^^^^^^^^^^^^^^^
 
 Let's now go back and check on our full design by using :yoscrypt:`hierarchy
--check -top example`.  By passing the ``-check`` option there we are also
+-check -top fifo`.  By passing the ``-check`` option there we are also
 telling the :cmd:ref:`hierarchy` command that if the design includes any
 non-blackbox modules without an implementation it should return an error.
 
 Note that if we tried to run this command now then we would get an error.  This
-is because we already removed all of the modules other than ``control``.  We
+is because we already removed all of the modules other than ``addr_gen``.  We
 could restart our shell session, but instead let's use two new commands:
 
 - :doc:`/cmd/design`, and
 - :doc:`/cmd/read_verilog`.
 
-.. literalinclude:: /code_examples/example_synth/example.out
+.. literalinclude:: /code_examples/fifo/fifo.out
    :language: doscon
    :start-at: design -reset
-   :end-before: yosys> show
-   :caption: reloading ``example.v`` and running :yoscrypt:`hierarchy -check -top example`
+   :end-before: yosys> proc
+   :caption: reloading ``fifo.v`` and running :yoscrypt:`hierarchy -check -top fifo`
 
 Notice how this time we didn't see any of those `$abstract` modules?  That's
-because when we ran ``yosys example.v``, the first command Yosys called was
-:yoscrypt:`read_verilog -defer example.v`.  The ``-defer`` option there tells
+because when we ran ``yosys fifo.v``, the first command Yosys called was
+:yoscrypt:`read_verilog -defer fifo.v`.  The ``-defer`` option there tells
 :cmd:ref:`read_verilog` only read the abstract syntax tree and defer actual
 compilation to a later :cmd:ref:`hierarchy` command. This is useful in cases
-where the default parameters of modules yield invalid or not synthesizable code,
-which is why Yosys does this automatically and is one of the reasons why
-hierarchy should always be the first command after loading the design.  If we
-know that our design won't run into this issue, we can skip the ``-defer``.
+where the default parameters of modules yield invalid code which is not
+synthesizable. This is why Yosys defers compilation automatically and is one of
+the reasons why hierarchy should always be the first command after loading the
+design.  If we know that our design won't run into this issue, we can skip the
+``-defer``.
+
+.. TODO:: more on why :cmd:ref:`hierarchy` is important
 
 .. note::
 
    The number before a command's output increments with each command run.  Don't
    worry if your numbers don't match ours!  The output you are seeing comes from
    the same script that was used to generate the images in this document,
-   included in the source as ``example.ys``. There are extra commands being run
+   included in the source as ``fifo.ys``. There are extra commands being run
    which you don't see, but feel free to try them yourself, or play around with
    different commands.  You can always start over with a clean slate by calling
    ``exit`` or hitting ``ctrl+c`` (i.e. SIGINT) and re-launching the Yosys
    interactive terminal.
 
-.. figure:: /_images/code_examples/example_synth/example_hier.*
+We can also run :cmd:ref:`proc` now to finish off the full :ref:`synth_begin`.
+Because the design schematic is quite large, we will be showing just the data
+path for the ``rdata`` output.  If you would like to see the entire design for
+yourself, you can do so with :doc:`/cmd/show`.  Note that the :cmd:ref:`show`
+command only works with a single module, so you may need to call it with
+:yoscrypt:`show fifo`.
+
+.. figure:: /_images/code_examples/fifo/rdata_proc.*
    :class: width-helper
-   :name: example_hier
+   :name: rdata_proc
 
-   ``example`` module after :cmd:ref:`hierarchy`
+   ``rdata`` output after :cmd:ref:`proc`
 
-We can also run :cmd:ref:`proc` now, although we won't actually see any change
-in this top view.
+The ``fifo_reader`` block we can see there is the same as the
+:ref:`addr_gen_proc` that we looked at earlier.
 
-.. TODO:: more on why :cmd:ref:`hierarchy` is important
+.. TODO:: comment on ``$memrd``
 
 .. seealso:: Advanced usage docs for
    :doc:`/using_yosys/synthesis/proc`
@@ -215,12 +220,14 @@ In :cmd:ref:`synth_ice40` we get these:
    :name: synth_flatten
    :caption: ``flatten`` section
 
-First off is :cmd:ref:`synth_flatten`.  Flattening the design like this can
-allow for optimizations between modules which would otherwise be missed.  We
-will skip this command for now because it makes the design schematic quite
-large.  If you would like to see for yourself, you can do so with
-:doc:`/cmd/show`.  Note that the :cmd:ref:`show` command only works with a
-single module, so you may need to call it with :yoscrypt:`show example`.
+First off is :cmd:ref:`flatten`.  Flattening the design like this can
+allow for optimizations between modules which would otherwise be missed. 
+
+.. figure:: /_images/code_examples/fifo/rdata_flat.*
+   :class: width-helper
+   :name: rdata_flat
+
+   ``rdata`` module after :cmd:ref:`flatten`
 
 Depending on the target architecture, we might also see commands such as
 :cmd:ref:`tribuf` with the ``-logic`` option and :cmd:ref:`deminout`.  These
@@ -244,6 +251,7 @@ In the iCE40 flow we get all the following commands:
 
 .. literalinclude:: /cmd/synth_ice40.rst
    :language: yoscrypt
+   :linenos:
    :start-after: coarse:
    :end-before: map_ram:
    :dedent: