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write_verilog: support $buf and $barrier
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@ -1071,7 +1071,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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}
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if (cell->type == ID($_BUF_)) {
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if (cell->type.in(ID($buf), ID($_BUF_), ID($barrier))) {
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, cell->getPort(ID::Y));
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f << stringf(" = ");
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