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Explicitly create separate $mux cells

This commit is contained in:
Eddie Hung 2020-01-21 16:49:34 -08:00
parent 152dfd3dd4
commit 72e4540ca9
1 changed files with 2 additions and 2 deletions
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4
techlibs/common/techmap.v
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@ -151,13 +151,13 @@ module _90_shift_shiftx (A, B, Y);
// the LSB of B, after discarding the zeroed bits // the LSB of B, after discarding the zeroed bits
localparam len = 2**(B_WIDTH-1); localparam len = 2**(B_WIDTH-1);
localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH; localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH;
wire [len-1:0] T, F; wire [len-1:0] T, F, AA;
genvar i; genvar i;
for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin
assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2]; assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2];
assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}}; assign T[i/2 +: Y_WIDTH2] = (i + Y_WIDTH2 < A_WIDTH) ? A[i+Y_WIDTH2 +: Y_WIDTH2] : {Y_WIDTH2{extbit}};
assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2];
end end
wire [len-1:0] AA = B[CLOG2_Y_WIDTH] ? T : F;
wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}};
if (_TECHMAP_CELLTYPE_ == "$shift") if (_TECHMAP_CELLTYPE_ == "$shift")
$shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y)); $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y));