mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4131 from daglem/fix-initial-display
Restore sim output from initial $display
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commit
728110710e
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@ -185,6 +185,7 @@ struct SimInstance
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struct print_state_t
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{
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bool initial_done;
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Const past_trg;
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Const past_en;
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Const past_args;
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@ -350,6 +351,7 @@ struct SimInstance
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print.past_trg = Const(State::Sx, cell->getPort(ID::TRG).size());
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print.past_args = Const(State::Sx, cell->getPort(ID::ARGS).size());
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print.past_en = State::Sx;
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print.initial_done = false;
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}
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}
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@ -852,13 +854,14 @@ struct SimInstance
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bool triggered = false;
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Const trg = get_state(cell->getPort(ID::TRG));
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bool trg_en = cell->getParam(ID::TRG_ENABLE).as_bool();
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Const en = get_state(cell->getPort(ID::EN));
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Const args = get_state(cell->getPort(ID::ARGS));
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if (!en.as_bool())
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goto update_print;
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if (cell->getParam(ID::TRG_ENABLE).as_bool()) {
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if (trg.size() > 0 && trg_en) {
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Const trg_pol = cell->getParam(ID::TRG_POLARITY);
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for (int i = 0; i < trg.size(); i++) {
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bool pol = trg_pol[i] == State::S1;
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@ -868,7 +871,12 @@ struct SimInstance
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if (!pol && curr == State::S0 && past == State::S1)
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triggered = true;
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}
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} else if (trg_en) {
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// initial $print (TRG width = 0, TRG_ENABLE = true)
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if (!print.initial_done && en != print.past_en)
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triggered = true;
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} else {
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// always @(*) $print
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if (args != print.past_args || en != print.past_en)
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triggered = true;
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}
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@ -889,6 +897,7 @@ struct SimInstance
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print.past_trg = trg;
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print.past_en = en;
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print.past_args = args;
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print.initial_done = true;
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}
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if (check_assertions)
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