mirror of https://github.com/YosysHQ/yosys.git
Support asymmetric memories for verific frontend
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parent
ff785cdb46
commit
71072d1945
frontends/verific
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@ -974,6 +974,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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module->memories[memory->name] = memory;
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module->memories[memory->name] = memory;
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int number_of_bits = net->Size();
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int number_of_bits = net->Size();
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number_of_bits = 1 << ceil_log2(number_of_bits);
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int bits_in_word = number_of_bits;
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int bits_in_word = number_of_bits;
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FOREACH_PORTREF_OF_NET(net, si, pr) {
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FOREACH_PORTREF_OF_NET(net, si, pr) {
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if (pr->GetInst()->Type() == OPER_READ_PORT) {
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if (pr->GetInst()->Type() == OPER_READ_PORT) {
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@ -1265,9 +1266,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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int numchunks = int(inst->OutputSize()) / memory->width;
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int numchunks = int(inst->OutputSize()) / memory->width;
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int chunksbits = ceil_log2(numchunks);
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int chunksbits = ceil_log2(numchunks);
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if ((numchunks * memory->width) != int(inst->OutputSize()) || (numchunks & (numchunks - 1)) != 0)
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log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
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for (int i = 0; i < numchunks; i++)
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for (int i = 0; i < numchunks; i++)
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{
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{
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RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
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RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
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@ -1295,9 +1293,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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int numchunks = int(inst->Input2Size()) / memory->width;
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int numchunks = int(inst->Input2Size()) / memory->width;
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int chunksbits = ceil_log2(numchunks);
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int chunksbits = ceil_log2(numchunks);
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if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0)
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log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
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for (int i = 0; i < numchunks; i++)
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for (int i = 0; i < numchunks; i++)
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{
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{
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RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
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RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
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