diff --git a/README.md b/README.md
index 87d9730a4..7e6aba22b 100644
--- a/README.md
+++ b/README.md
@@ -607,7 +607,7 @@ following are used for building the website:
 PDFLaTeX, included with most LaTeX distributions, is also needed during the
 build process for the website.  Or, run the following:
 
-	$ sudo apt install texlive-latex-base texlive-latex-extra
+	$ sudo apt install texlive-latex-base texlive-latex-extra latexmk
 
 The Python package, Sphinx, is needed along with those listed in
 `docs/source/requirements.txt`:
diff --git a/docs/source/using_yosys/memory_mapping.rst b/docs/source/using_yosys/memory_mapping.rst
index 41654a0c5..21cea5319 100644
--- a/docs/source/using_yosys/memory_mapping.rst
+++ b/docs/source/using_yosys/memory_mapping.rst
@@ -198,8 +198,8 @@ Synchronous SDP with undefined collision behavior
 		if (read_enable) begin
 			read_data <= mem[read_addr];
 		
-		// 👇 this if block 👇
 		if (write_enable && read_addr == write_addr)
+			// this if block
 			read_data <= 'x;
 		end
 	end
diff --git a/docs/source/using_yosys/more_scripting/opt_passes.rst b/docs/source/using_yosys/more_scripting/opt_passes.rst
index 15f2e20af..f8b558854 100644
--- a/docs/source/using_yosys/more_scripting/opt_passes.rst
+++ b/docs/source/using_yosys/more_scripting/opt_passes.rst
@@ -128,7 +128,7 @@ is produced.
 The ``opt_rmdff`` pass
 ~~~~~~~~~~~~~~~~~~~~~~
 
-.. todo:: The ``opt_rmdff`` pass doesn't exist anymore?
+.. todo:: Update to ``opt_dff``
 
 This pass identifies single-bit d-type flip-flops (``$_DFF_``, ``$dff``, and
 ``$adff`` cells) with a constant data input and replaces them with a constant
diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst
index fa356e785..78fa47ba4 100644
--- a/docs/source/yosys_internals/formats/rtlil_rep.rst
+++ b/docs/source/yosys_internals/formats/rtlil_rep.rst
@@ -59,7 +59,7 @@ RTLIL identifiers
 
 All identifiers in RTLIL (such as module names, port names, signal names, cell
 types, etc.) follow the following naming convention: they must either start with
-a backslash (\) or a dollar sign ($).
+a backslash (``\``) or a dollar sign (``$``).
 
 Identifiers starting with a backslash are public visible identifiers. Usually
 they originate from one of the HDL input files. For example the signal name
@@ -74,7 +74,7 @@ This has three advantages:
 -  First, it is impossible that an auto-generated identifier collides with an
    identifier that was provided by the user.
 
-.. todo:: does opt_rmunused (still?) exist?
+.. todo:: ``opt_clean`` (or clean), also ``-purge``
 
 -  Second, the information about which identifiers were originally provided by
    the user is always available which can help guide some optimizations. For
@@ -86,7 +86,7 @@ This has three advantages:
    names is deferred to one central location. Internally auto-generated names
    that may hold important information for Yosys developers can be used without
    disturbing external tools. For example the Verilog backend assigns names in
-   the form \_integer\_.
+   the form ``_123_``.
 
 Whitespace and control characters (any character with an ASCII code 32 or less)
 are not allowed in RTLIL identifiers; most frontends and backends cannot support
@@ -158,7 +158,7 @@ An ``RTLIL::Wire`` object has the following properties:
 
 -  The wire name
 -  A list of attributes
--  A width (buses are just wires with a width > 1)
+-  A width (buses are just wires with a width more than 1)
 -  Bus direction (MSB to LSB or vice versa)
 -  Lowest valid bit index (LSB or MSB depending on bus direction)
 -  If the wire is a port: port number and direction (input/output/inout)
@@ -167,7 +167,7 @@ As with modules, the attributes can be Verilog attributes imported by the
 Verilog frontend or attributes assigned by passes.
 
 In Yosys, busses (signal vectors) are represented using a single wire object
-with a width > 1. So Yosys does not convert signal vectors to individual
+with a width more than 1. So Yosys does not convert signal vectors to individual
 signals. This makes some aspects of RTLIL more complex but enables Yosys to be
 used for coarse grain synthesis where the cells of the target architecture
 operate on entire signal vectors instead of single bit wires.