mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #702 from smunaut/min_ce_use
Add option to only use DFFE is the resulting E signal would be use > N times
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commit
70c417174d
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@ -263,10 +263,14 @@ struct Dff2dffePass : public Pass {
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log("more feedback paths to $dffe cells. It also works on gate-level cells such as\n");
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log("$_DFF_P_, $_DFF_N_ and $_MUX_.\n");
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log("\n");
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log(" -unmap\n");
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log(" -unmap");
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log(" operate in the opposite direction: replace $dffe cells with combinations\n");
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log(" of $dff and $mux cells. the options below are ignore in unmap mode.\n");
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log("\n");
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log(" -unmap-mince N\n");
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log(" Same as -unmap but only unmap $dffe where the clock enable port\n");
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log(" signal is used by less $dffe than the specified number\n");
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log("\n");
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log(" -direct <internal_gate_type> <external_gate_type>\n");
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log(" map directly to external gate type. <internal_gate_type> can\n");
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log(" be any internal gate-level FF cell (except $_DFFE_??_). the\n");
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@ -289,6 +293,7 @@ struct Dff2dffePass : public Pass {
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log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
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bool unmap_mode = false;
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int min_ce_use = -1;
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dict<IdString, IdString> direct_dict;
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size_t argidx;
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@ -297,6 +302,11 @@ struct Dff2dffePass : public Pass {
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unmap_mode = true;
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continue;
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}
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if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) {
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unmap_mode = true;
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min_ce_use = std::stoi(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-direct" && argidx + 2 < args.size()) {
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string direct_from = RTLIL::escape_id(args[++argidx]);
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string direct_to = RTLIL::escape_id(args[++argidx]);
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@ -343,8 +353,21 @@ struct Dff2dffePass : public Pass {
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if (!mod->has_processes_warn())
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{
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if (unmap_mode) {
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SigMap sigmap(mod);
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for (auto cell : mod->selected_cells()) {
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if (cell->type == "$dffe") {
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if (min_ce_use >= 0) {
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int ce_use = 0;
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for (auto cell_other : mod->selected_cells()) {
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if (cell_other->type != cell->type)
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continue;
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if (sigmap(cell->getPort("\\EN")) == sigmap(cell_other->getPort("\\EN")))
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ce_use++;
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}
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if (ce_use >= min_ce_use)
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continue;
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}
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RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort("\\D")));
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mod->addDff(NEW_ID, cell->getPort("\\CLK"), tmp, cell->getPort("\\Q"), cell->getParam("\\CLK_POLARITY").as_bool());
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if (cell->getParam("\\EN_POLARITY").as_bool())
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@ -355,6 +378,18 @@ struct Dff2dffePass : public Pass {
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continue;
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}
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if (cell->type.substr(0, 7) == "$_DFFE_") {
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if (min_ce_use >= 0) {
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int ce_use = 0;
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for (auto cell_other : mod->selected_cells()) {
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if (cell_other->type != cell->type)
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continue;
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if (sigmap(cell->getPort("\\E")) == sigmap(cell_other->getPort("\\E")))
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ce_use++;
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}
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if (ce_use >= min_ce_use)
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continue;
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}
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bool clk_pol = cell->type.substr(7, 1) == "P";
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bool en_pol = cell->type.substr(8, 1) == "P";
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RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
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@ -69,6 +69,10 @@ struct SynthIce40Pass : public ScriptPass
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log(" -nodffe\n");
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log(" do not use SB_DFFE* cells in output netlist\n");
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log("\n");
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log(" -dffe_min_ce_use <min_ce_use>\n");
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log(" do not use SB_DFFE* cells if the resulting CE line would go to less\n");
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log(" than min_ce_use SB_DFFE*in output netlist\n");
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log("\n");
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log(" -nobram\n");
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log(" do not use SB_RAM40_4K* cells in output netlist\n");
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log("\n");
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@ -87,6 +91,7 @@ struct SynthIce40Pass : public ScriptPass
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string top_opt, blif_file, edif_file, json_file;
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bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
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int min_ce_use;
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void clear_flags() YS_OVERRIDE
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{
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@ -96,6 +101,7 @@ struct SynthIce40Pass : public ScriptPass
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json_file = "";
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nocarry = false;
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nodffe = false;
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min_ce_use = -1;
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nobram = false;
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flatten = true;
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retime = false;
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@ -155,6 +161,10 @@ struct SynthIce40Pass : public ScriptPass
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nodffe = true;
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continue;
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}
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if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
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min_ce_use = std::stoi(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-nobram") {
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nobram = true;
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continue;
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@ -228,6 +238,10 @@ struct SynthIce40Pass : public ScriptPass
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run("dffsr2dff");
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if (!nodffe)
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run("dff2dffe -direct-match $_DFF_*");
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if (min_ce_use >= 0) {
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run("opt_merge");
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run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
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}
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run("techmap -D NO_LUT -map +/ice40/cells_map.v");
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run("opt_expr -mux_undef");
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run("simplemap");
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