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Merge pull request #1325 from YosysHQ/eddie/sat_init 

In sat: 'x' in init attr should be ignored
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Clifford Wolf 2019-08-28 00:18:14 +02:00 committed by GitHub
parent d361f5ab79 28133432be
commit 70c0cddb1e
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2 changed files with 8 additions and 2 deletions
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2
passes/sat/sat.cc
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@ -268,7 +268,7 @@ struct SatHelper
RTLIL::SigSpec removed_bits; RTLIL::SigSpec removed_bits;
for (int i = 0; i < lhs.size(); i++) { for (int i = 0; i < lhs.size(); i++) {
RTLIL::SigSpec bit = lhs.extract(i, 1); RTLIL::SigSpec bit = lhs.extract(i, 1);
if (!satgen.initial_state.check_all(bit)) { if (rhs[i] == State::Sx || !satgen.initial_state.check_all(bit)) {
removed_bits.append(bit); removed_bits.append(bit);
lhs.remove(i, 1); lhs.remove(i, 1);
rhs.remove(i, 1); rhs.remove(i, 1);

8
tests/sat/initval.v
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@ -1,6 +1,7 @@
module test(input clk, input [3:0] bar, output [3:0] foo); module test(input clk, input [3:0] bar, output [3:0] foo, asdf);
reg [3:0] foo = 0; reg [3:0] foo = 0;
reg [3:0] last_bar = 0; reg [3:0] last_bar = 0;
reg [3:0] asdf = 4'b1xxx;
always @* always @*
foo[1:0] <= bar[1:0]; foo[1:0] <= bar[1:0];
@ -11,5 +12,10 @@ module test(input clk, input [3:0] bar, output [3:0] foo);
always @(posedge clk) always @(posedge clk)
last_bar <= bar; last_bar <= bar;
always @(posedge clk)
asdf[3] <= bar[3];
always @*
asdf[2:0] = 3'b111;
assert property (foo == {last_bar[3:2], bar[1:0]}); assert property (foo == {last_bar[3:2], bar[1:0]});
endmodule endmodule