mirror of https://github.com/YosysHQ/yosys.git
Improved width extension with regard to undef propagation
This commit is contained in:
Clifford Wolf
parent
f839b842a2
commit
6fcbc79b5c
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@ -83,6 +83,56 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
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return sig;
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}
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// helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
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static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
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{
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if (width <= sig.width) {
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sig.extend(width, is_signed);
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return;
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}
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std::stringstream sstr;
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sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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cell->name = sstr.str();
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cell->type = "$pos";
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current_module->cells[cell->name] = cell;
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RTLIL::Wire *wire = new RTLIL::Wire;
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wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
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wire->name = cell->name + "_Y";
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wire->width = width;
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current_module->wires[wire->name] = wire;
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RTLIL::SigChunk chunk;
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chunk.wire = wire;
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chunk.width = wire->width;
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chunk.offset = 0;
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RTLIL::SigSpec new_sig;
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new_sig.chunks.push_back(chunk);
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new_sig.width = chunk.width;
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if (that != NULL)
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for (auto &attr : that->attributes) {
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if (attr.second->type != AST_CONSTANT)
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log_error("Attribute `%s' with non-constant value at %s:%d!\n",
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attr.first.c_str(), that->filename.c_str(), that->linenum);
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cell->attributes[attr.first].str = attr.second->str;
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cell->attributes[attr.first].bits = attr.second->bits;
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}
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.width);
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cell->connections["\\A"] = sig;
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cell->parameters["\\Y_WIDTH"] = width;
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cell->connections["\\Y"] = new_sig;
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sig = new_sig;
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}
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// helper function for creating RTLIL code for binary operations
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static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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@ -943,7 +993,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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int width = arg.width;
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if (width_hint > 0) {
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width = width_hint;
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arg.extend(width, is_signed);
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widthExtend(this, arg, width, is_signed);
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}
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return uniop2rtlil(this, type_name, width, arg);
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}
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@ -972,7 +1022,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
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{
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RTLIL::SigSpec arg = children[0]->genRTLIL();
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RTLIL::SigSpec sig = uniop2rtlil(this, type_name, 1, arg);
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RTLIL::SigSpec sig = uniop2rtlil(this, type_name, std::max(width_hint, 1), arg);
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return sig;
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}
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@ -981,7 +1031,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
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{
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RTLIL::SigSpec arg = children[0]->genRTLIL();
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RTLIL::SigSpec sig = arg.width > 1 ? uniop2rtlil(this, type_name, 1, arg) : arg;
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RTLIL::SigSpec sig = arg.width > 1 ? uniop2rtlil(this, type_name, std::max(width_hint, 1), arg) : arg;
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return sig;
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}
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@ -1008,12 +1058,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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if (0) { case AST_GE: type_name = "$ge"; }
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if (0) { case AST_GT: type_name = "$gt"; }
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{
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int width = std::max(width_hint, 1);
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width_hint = -1, sign_hint = true;
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children[0]->detectSignWidthWorker(width_hint, sign_hint);
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children[1]->detectSignWidthWorker(width_hint, sign_hint);
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RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
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RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
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RTLIL::SigSpec sig = binop2rtlil(this, type_name, 1, left, right);
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RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
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return sig;
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}
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@ -1054,14 +1105,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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{
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RTLIL::SigSpec left = children[0]->genRTLIL();
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RTLIL::SigSpec right = children[1]->genRTLIL();
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return binop2rtlil(this, type_name, 1, left, right);
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return binop2rtlil(this, type_name, std::max(width_hint, 1), left, right);
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}
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// generate cells for unary operations: $logic_not
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case AST_LOGIC_NOT:
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{
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RTLIL::SigSpec arg = children[0]->genRTLIL();
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return uniop2rtlil(this, "$logic_not", 1, arg);
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return uniop2rtlil(this, "$logic_not", std::max(width_hint, 1), arg);
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}
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// generate multiplexer for ternary operator (aka ?:-operator)
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@ -1079,8 +1130,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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int width = std::max(val1.width, val2.width);
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is_signed = children[1]->is_signed && children[2]->is_signed;
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val1.extend(width, is_signed);
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val2.extend(width, is_signed);
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widthExtend(this, val1, width, is_signed);
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widthExtend(this, val2, width, is_signed);
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return mux2rtlil(this, cond, val1, val2);
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}
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@ -1271,7 +1322,7 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, RTLIL::SigSpec *subst_from, RT
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genRTLIL_subst_to = backup_subst_to;
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if (width >= 0)
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sig.extend(width, is_signed);
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widthExtend(this, sig, width, is_signed);
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return sig;
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}
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161
kernel/calc.cc
161
kernel/calc.cc
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@ -17,10 +17,22 @@
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*
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*/
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#include "kernel/log.h"
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#include "kernel/rtlil.h"
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#include "libs/bigint/BigIntegerLibrary.hh"
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#include <assert.h>
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static void extend(RTLIL::Const &arg, int width, bool is_signed)
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{
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RTLIL::State padding = RTLIL::State::S0;
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if (arg.bits.size() > 0 && (is_signed || arg.bits.back() > RTLIL::State::S1))
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padding = arg.bits.back();
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while (int(arg.bits.size()) < width)
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arg.bits.push_back(padding);
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}
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static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
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{
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BigInteger result = 0, this_bit = 1;
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@ -105,8 +117,7 @@ RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, boo
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result_len = arg1.bits.size();
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RTLIL::Const arg1_ext = arg1;
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while (int(arg1_ext.bits.size()) < result_len)
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arg1_ext.bits.push_back(signed1 && arg1_ext.bits.size() ? arg1_ext.bits.back() : RTLIL::State::S0);
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extend(arg1_ext, result_len, signed1);
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (size_t i = 0; i < size_t(result_len); i++) {
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@ -127,11 +138,8 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
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if (result_len < 0)
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result_len = std::max(arg1.bits.size(), arg2.bits.size());
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while (int(arg1.bits.size()) < result_len)
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arg1.bits.push_back(signed1 && arg1.bits.size() ? arg1.bits.back() : RTLIL::State::S0);
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while (int(arg2.bits.size()) < result_len)
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arg2.bits.push_back(signed2 && arg2.bits.size() ? arg2.bits.back() : RTLIL::State::S0);
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extend(arg1, result_len, signed1);
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extend(arg2, result_len, signed2);
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RTLIL::Const result(RTLIL::State::Sx, result_len);
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for (size_t i = 0; i < size_t(result_len); i++) {
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@ -163,86 +171,90 @@ RTLIL::Const RTLIL::const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg
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return logic_wrapper(logic_xnor, arg1, arg2, signed1, signed2, result_len);
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}
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static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), const RTLIL::Const &arg1)
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static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), const RTLIL::Const &arg1, int result_len)
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{
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RTLIL::State temp = initial;
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for (size_t i = 0; i < arg1.bits.size(); i++)
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temp = logic_func(temp, arg1.bits[i]);
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return RTLIL::Const(temp);
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RTLIL::Const result(temp);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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return result;
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}
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RTLIL::Const RTLIL::const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int)
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RTLIL::Const RTLIL::const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
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{
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return logic_reduce_wrapper(RTLIL::State::S1, logic_and, arg1);
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return logic_reduce_wrapper(RTLIL::State::S1, logic_and, arg1, result_len);
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}
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RTLIL::Const RTLIL::const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int)
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RTLIL::Const RTLIL::const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
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{
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return logic_reduce_wrapper(RTLIL::State::S0, logic_or, arg1);
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return logic_reduce_wrapper(RTLIL::State::S0, logic_or, arg1, result_len);
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}
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RTLIL::Const RTLIL::const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int)
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RTLIL::Const RTLIL::const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
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{
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return logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1);
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return logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len);
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}
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RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int)
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RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
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{
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RTLIL::Const not_y = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1);
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if (not_y.bits.front() == RTLIL::State::S0) return RTLIL::State::S1;
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if (not_y.bits.front() == RTLIL::State::S1) return RTLIL::State::S0;
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return RTLIL::State::Sx;
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RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len);
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if (!buffer.bits.empty()) {
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if (buffer.bits.front() == RTLIL::State::S0)
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buffer.bits.front() = RTLIL::State::S1;
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else if (buffer.bits.front() == RTLIL::State::S1)
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buffer.bits.front() = RTLIL::State::S0;
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}
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return buffer;
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}
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RTLIL::Const RTLIL::const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int)
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RTLIL::Const RTLIL::const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
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{
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return logic_reduce_wrapper(RTLIL::State::S0, logic_or, arg1);
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return logic_reduce_wrapper(RTLIL::State::S0, logic_or, arg1, result_len);
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}
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RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int)
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RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
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{
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int undef_bit_pos_a = -1;
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BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
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RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
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if (a.isZero()) {
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if (undef_bit_pos_a >= 0)
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return RTLIL::Const(RTLIL::State::Sx);
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return RTLIL::Const(RTLIL::State::S1);
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}
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return RTLIL::Const(RTLIL::State::S0);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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return result;
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}
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RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
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RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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{
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int undef_bit_pos_a = -1, undef_bit_pos_b = -1;
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BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
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BigInteger b = const2big(arg2, signed2, undef_bit_pos_b);
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if (a.isZero() || b.isZero()) {
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if (undef_bit_pos_a >= 0 && undef_bit_pos_b >= 0)
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return RTLIL::Const(RTLIL::State::Sx);
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return RTLIL::Const(RTLIL::State::S0);
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}
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RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::Const result(logic_and(bit_a, bit_b));
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return RTLIL::Const(RTLIL::State::S1);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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return result;
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}
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RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
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RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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{
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int undef_bit_pos_a = -1, undef_bit_pos_b = -1;
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BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
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BigInteger b = const2big(arg2, signed2, undef_bit_pos_b);
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if (a.isZero() && b.isZero()) {
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if (undef_bit_pos_a >= 0 || undef_bit_pos_b >= 0)
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return RTLIL::Const(RTLIL::State::Sx);
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return RTLIL::Const(RTLIL::State::S0);
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}
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RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
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RTLIL::Const result(logic_or(bit_a, bit_b));
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return RTLIL::Const(RTLIL::State::S1);
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while (int(result.bits.size()) < result_len)
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result.bits.push_back(RTLIL::State::S0);
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return result;
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}
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static RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, int direction, int result_len)
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@ -273,16 +285,14 @@ static RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &ar
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RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
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{
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RTLIL::Const arg1_ext = arg1;
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while (int(arg1_ext.bits.size()) < result_len)
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arg1_ext.bits.push_back(signed1 && arg1_ext.bits.size() ? arg1_ext.bits.back() : RTLIL::State::S0);
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extend(arg1_ext, result_len, signed1);
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return const_shift(arg1_ext, arg2, false, -1, result_len);
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}
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RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
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{
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RTLIL::Const arg1_ext = arg1;
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while (int(arg1_ext.bits.size()) < result_len)
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arg1_ext.bits.push_back(signed1 && arg1_ext.bits.size() ? arg1_ext.bits.back() : RTLIL::State::S0);
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extend(arg1_ext, result_len, signed1);
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return const_shift(arg1_ext, arg2, false, +1, result_len);
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}
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@ -300,46 +310,70 @@ RTLIL::Const RTLIL::const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg
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return const_shift(arg1, arg2, true, +1, result_len);
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}
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RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
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RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
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{
|
||||
int undef_bit_pos = -1;
|
||||
bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
|
||||
return RTLIL::Const(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
|
||||
while (int(result.bits.size()) < result_len)
|
||||
result.bits.push_back(RTLIL::State::S0);
|
||||
return result;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
|
||||
RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
{
|
||||
int undef_bit_pos = -1;
|
||||
bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
|
||||
return RTLIL::Const(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
|
||||
while (int(result.bits.size()) < result_len)
|
||||
result.bits.push_back(RTLIL::State::S0);
|
||||
return result;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
|
||||
RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
{
|
||||
int undef_bit_pos = -1;
|
||||
bool y = const2big(arg1, signed1, undef_bit_pos) == const2big(arg2, signed2, undef_bit_pos);
|
||||
return RTLIL::Const(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
|
||||
while (int(result.bits.size()) < result_len)
|
||||
result.bits.push_back(RTLIL::State::S0);
|
||||
return result;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
|
||||
RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
{
|
||||
int undef_bit_pos = -1;
|
||||
bool y = const2big(arg1, signed1, undef_bit_pos) != const2big(arg2, signed2, undef_bit_pos);
|
||||
return RTLIL::Const(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
|
||||
while (int(result.bits.size()) < result_len)
|
||||
result.bits.push_back(RTLIL::State::S0);
|
||||
return result;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
|
||||
RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
{
|
||||
int undef_bit_pos = -1;
|
||||
bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
|
||||
return RTLIL::Const(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
|
||||
while (int(result.bits.size()) < result_len)
|
||||
result.bits.push_back(RTLIL::State::S0);
|
||||
return result;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int)
|
||||
RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
{
|
||||
int undef_bit_pos = -1;
|
||||
bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
|
||||
return RTLIL::Const(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
|
||||
while (int(result.bits.size()) < result_len)
|
||||
result.bits.push_back(RTLIL::State::S0);
|
||||
return result;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
|
||||
|
|
@ -416,16 +450,15 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
|
|||
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
|
||||
{
|
||||
RTLIL::Const arg1_ext = arg1;
|
||||
while (int(arg1_ext.bits.size()) < result_len)
|
||||
arg1_ext.bits.push_back(signed1 && arg1_ext.bits.size() ? arg1_ext.bits.back() : RTLIL::State::S0);
|
||||
extend(arg1_ext, result_len, signed1);
|
||||
|
||||
return arg1_ext;
|
||||
}
|
||||
|
||||
RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
|
||||
{
|
||||
RTLIL::Const arg1_ext = arg1;
|
||||
while (int(arg1_ext.bits.size()) < result_len)
|
||||
arg1_ext.bits.push_back(signed1 && arg1_ext.bits.size() ? arg1_ext.bits.back() : RTLIL::State::S0);
|
||||
extend(arg1_ext, result_len, signed1);
|
||||
|
||||
RTLIL::Const zero(RTLIL::State::S0, 1);
|
||||
return RTLIL::const_sub(zero, arg1_ext, false, signed1, result_len);
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ struct SatGen
|
|||
if (cell->type == "$logic_not")
|
||||
ez->SET(ez->NOT(ez->expression(ez->OpOr, a)), y.at(0));
|
||||
for (size_t i = 1; i < y.size(); i++)
|
||||
ez->SET(0, y.at(0));
|
||||
ez->SET(ez->FALSE, y.at(i));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -200,7 +200,7 @@ struct SatGen
|
|||
else
|
||||
ez->SET(ez->expression(ez->OpOr, a, b), y.at(0));
|
||||
for (size_t i = 1; i < y.size(); i++)
|
||||
ez->SET(0, y.at(0));
|
||||
ez->SET(ez->FALSE, y.at(i));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -223,7 +223,7 @@ struct SatGen
|
|||
if (cell->type == "$gt")
|
||||
ez->SET(is_signed ? ez->vec_gt_signed(a, b) : ez->vec_gt_unsigned(a, b), y.at(0));
|
||||
for (size_t i = 1; i < y.size(); i++)
|
||||
ez->SET(0, y.at(0));
|
||||
ez->SET(ez->FALSE, y.at(i));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ parameter A_WIDTH = 1;
|
|||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
|
|
@ -274,7 +274,7 @@ parameter A_WIDTH = 1;
|
|||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
|
|
@ -303,7 +303,7 @@ parameter A_WIDTH = 1;
|
|||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
|
|
@ -333,7 +333,7 @@ parameter A_WIDTH = 1;
|
|||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
|
|
@ -365,7 +365,7 @@ parameter A_WIDTH = 1;
|
|||
parameter Y_WIDTH = 1;
|
||||
|
||||
input [A_WIDTH-1:0] A;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire [A_WIDTH-1:0] buffer;
|
||||
|
||||
|
|
@ -699,7 +699,7 @@ parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire carry, carry_sign;
|
||||
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
|
||||
|
|
@ -748,7 +748,7 @@ parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire carry, carry_sign;
|
||||
wire [WIDTH-1:0] A_buf, B_buf, Y_buf;
|
||||
|
|
@ -797,7 +797,7 @@ parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire carry, carry_sign;
|
||||
wire [WIDTH-1:0] A_buf, B_buf;
|
||||
|
|
@ -822,7 +822,7 @@ parameter WIDTH = A_WIDTH > B_WIDTH ? A_WIDTH : B_WIDTH;
|
|||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
wire carry, carry_sign;
|
||||
wire [WIDTH-1:0] A_buf, B_buf;
|
||||
|
|
@ -845,7 +845,7 @@ parameter Y_WIDTH = 1;
|
|||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
\$le #(
|
||||
.A_SIGNED(B_SIGNED),
|
||||
|
|
@ -872,7 +872,7 @@ parameter Y_WIDTH = 1;
|
|||
|
||||
input [A_WIDTH-1:0] A;
|
||||
input [B_WIDTH-1:0] B;
|
||||
output Y;
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
\$lt #(
|
||||
.A_SIGNED(B_SIGNED),
|
||||
|
|
|
|||
Loading…
Reference in New Issue