mirror of https://github.com/YosysHQ/yosys.git
Fixed port ordering in "splitnets" cmd
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6f9a6fd783
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@ -50,7 +50,7 @@ struct SplitnetsWorker
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new_wire_name += format.substr(1, 1);
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new_wire_name += format.substr(1, 1);
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RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
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RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
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new_wire->port_id = wire->port_id;
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new_wire->port_id = wire->port_id ? wire->port_id + offset : 0;
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new_wire->port_input = wire->port_input;
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new_wire->port_input = wire->port_input;
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new_wire->port_output = wire->port_output;
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new_wire->port_output = wire->port_output;
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@ -130,14 +130,24 @@ struct SplitnetsPass : public Pass {
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules_)
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for (auto module : design->selected_modules())
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{
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{
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RTLIL::Module *module = mod_it.second;
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if (!design->selected(module))
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continue;
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SplitnetsWorker worker;
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SplitnetsWorker worker;
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if (flag_ports)
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{
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int normalized_port_factor = 0;
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for (auto wire : module->wires())
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if (wire->port_id != 0) {
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normalized_port_factor = std::max(normalized_port_factor, wire->port_id+1);
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normalized_port_factor = std::max(normalized_port_factor, GetSize(wire)+1);
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}
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for (auto wire : module->wires())
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wire->port_id *= normalized_port_factor;
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}
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if (flag_driver)
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if (flag_driver)
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{
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{
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CellTypes ct(design);
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CellTypes ct(design);
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@ -194,6 +204,7 @@ struct SplitnetsPass : public Pass {
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delete_wires.insert(it.first);
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delete_wires.insert(it.first);
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module->remove(delete_wires);
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module->remove(delete_wires);
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if (flag_ports)
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module->fixup_ports();
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module->fixup_ports();
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}
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}
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}
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}
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