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Removed $aconst cell type

This commit is contained in:
Clifford Wolf 2016-08-30 19:09:56 +02:00
parent a8124c137e
commit 6f41e5277d
7 changed files with 8 additions and 21 deletions
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6
frontends/ast/genrtlil.cc
View File

@ -754,7 +754,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
break;
case AST_FCALL:
if (str == "\\$anyconst" || str == "\\$aconst") {
if (str == "\\$anyconst") {
if (GetSize(children) == 1) {
while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
if (children[0]->type != AST_CONSTANT)
@ -1447,9 +1447,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} break;
case AST_FCALL: {
if (str == "\\$anyconst" || str == "\\$aconst")
if (str == "\\$anyconst")
{
string myid = stringf("%s$%d", RTLIL::unescape_id(str).c_str(), autoidx++);
string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
int width = width_hint;
if (GetSize(children) > 1)

4
frontends/ast/simplify.cc
View File

@ -1672,8 +1672,8 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
// $anyconst and $aconst are mapped in AstNode::genRTLIL()
if (str == "\\$anyconst" || str == "\\$aconst")
// $anyconst is mapped in AstNode::genRTLIL()
if (str == "\\$anyconst")
return false;
if (str == "\\$clog2")

2
frontends/verilog/verilog_parser.y
View File

@ -1229,7 +1229,7 @@ rvalue:
$$ = new AstNode(AST_IDENTIFIER, $2);
$$->str = *$1;
delete $1;
if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$aconst"))
if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst"))
$$->type = AST_FCALL;
} |
hierarchical_id non_opt_multirange {

1
kernel/celltypes.h
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@ -118,7 +118,6 @@ struct CellTypes
setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$aconst", pool<RTLIL::IdString>(), {Y}, true);
setup_type("$equiv", {A, B}, {Y}, true);
}

2
kernel/rtlil.cc
View File

@ -1030,7 +1030,7 @@ namespace {
return;
}
if (cell->type.in("$aconst", "$anyconst")) {
if (cell->type == "$anyconst") {
port("\\Y", param("\\WIDTH"));
check_expected();
return;

2
manual/CHAPTER_CellLib.tex
View File

@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
using the {\tt abc} pass.
\begin{fixme}
Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$aconst}, and {\tt \$anyconst} cells.
Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, and {\tt \$anyconst} cells.
\end{fixme}
\begin{fixme}

12
techlibs/common/simlib.v
View File

@ -1322,18 +1322,6 @@ endmodule
// --------------------------------------------------------
module \$aconst (Y);
parameter WIDTH = 0;
output [WIDTH-1:0] Y;
assign Y = 'bx;
endmodule
// --------------------------------------------------------
module \$anyconst (Y);
parameter WIDTH = 0;