riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1715 from boqwxp/master 

Closes #1714. Fix make failure when NDEBUG=1.
This commit is contained in:
Eddie Hung 2020-02-22 11:29:22 -08:00 committed by GitHub
parent 760096e8d2 750e7a9a54
commit 6edca05793
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/abc9_ops.cc
View File

@ -752,13 +752,11 @@ void reintegrate(RTLIL::Module *module)
continue; continue;
} }
#ifndef NDEBUG
RTLIL::Module* box_module = design->module(existing_cell->type); RTLIL::Module* box_module = design->module(existing_cell->type);
IdString derived_type = box_module->derive(design, existing_cell->parameters); IdString derived_type = box_module->derive(design, existing_cell->parameters);
RTLIL::Module* derived_module = design->module(derived_type); RTLIL::Module* derived_module = design->module(derived_type);
log_assert(derived_module); log_assert(derived_module);
log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int())); log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
#endif
mapped_cell->type = existing_cell->type; mapped_cell->type = existing_cell->type;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type); RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);