riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add more muxpack tests, with overlapping entries

This commit is contained in:
Eddie Hung 2019-06-21 11:45:53 -07:00
parent 641b86d25f
commit 6ec8160981
2 changed files with 84 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
tests/various/muxpack.v
View File

@ -187,7 +187,9 @@ module case_nonexclusive_select (
); );
always @* begin always @* begin
case (x) case (x)
0, 2: o = b; //0, 2: o = b;
0: o = b;
2: o = b;
1: o = c; 1: o = c;
default: begin default: begin
o = a; o = a;
@ -197,3 +199,54 @@ module case_nonexclusive_select (
endcase endcase
end end
endmodule endmodule
module case_nonoverlap (
input wire [2:0] x,
input wire a, b, c, d, e, f, g,
output reg o
);
always @* begin
case (x)
//0, 2: o = b; // Creates $reduce_or
//0: o = b; 2: o = b; // Creates $reduce_or
0: o = b;
2: o = f;
1: o = c;
default:
case (x)
//3, 4: o = d; // Creates $reduce_or
//3: o = d; 4: o = d; // Creates $reduce_or
3: o = d;
4: o = g;
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule
module case_overlap (
input wire [2:0] x,
input wire a, b, c, d, e, f, g,
output reg o
);
always @* begin
case (x)
//0, 2: o = b; // Creates $reduce_or
//0: o = b; 2: o = b; // Creates $reduce_or
0: o = b;
2: o = f;
1: o = c;
default:
case (x)
//3, 4: o = d; // Creates $reduce_or
//3: o = d; 4: o = d; // Creates $reduce_or
2: o = 1'b1; // Overlaps with previous $pmux
3: o = d;
4: o = g;
5: o = e;
default: o = 1'b0;
endcase
endcase
end
endmodule

30
tests/various/muxpack.ys
View File

@ -212,3 +212,33 @@ design -import gold -as gold
design -import gate -as gate design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_nonoverlap
prep
design -save gold
muxpack
opt
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top case_overlap
prep
design -save gold
muxpack
#opt # Do not opt otherwise $pmux's overlapping entry will get removed
stat
select -assert-count 0 t:$mux
select -assert-count 1 t:$pmux
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter