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Combine tests to check multiple clock domains

This commit is contained in:
Eddie Hung 2020-01-02 14:38:59 -08:00
parent a051801b72
commit 6e866030c2
1 changed files with 10 additions and 33 deletions
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43
tests/arch/xilinx/abc9_dff.ys
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@ -1,55 +1,32 @@
read_verilog <<EOT read_verilog <<EOT
module top(input C, D, output [3:0] Q); module top(input C, D, output [7:0] Q);
FDRE fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0])); FDRE fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
FDSE fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1])); FDSE fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
FDCE fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2])); FDCE fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
FDPE fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3])); FDPE fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
FDRE_1 fd5(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[4]));
FDSE_1 fd6(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[5]));
FDCE_1 fd7(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[6]));
FDPE_1 fd8(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[7]));
endmodule endmodule
EOT EOT
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt design -load postopt
select -assert-none t:FD* select -assert-none t:FD*
design -reset design -reset
read_verilog <<EOT read_verilog <<EOT
module top(input C, D, output [3:0] Q); module top(input C, D, output [7:0] Q);
FDRE fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0])); FDRE fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
FDSE fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1])); FDSE fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
FDCE fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2])); FDCE fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
FDPE fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3])); FDPE fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
FDRE_1 fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4]));
FDSE_1 fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5]));
FDCE_1 fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6]));
FDPE_1 fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7]));
endmodule endmodule
EOT EOT
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt design -load postopt
select -assert-none t:FD* select -assert-none t:FD*
design -reset
read_verilog <<EOT
module top(input C, D, output [3:0] Q);
FDRE_1 fd1(.C(C), .CE(1'b1), .D(D), .R(1'b1), .Q(Q[0]));
FDSE_1 fd2(.C(C), .CE(1'b1), .D(D), .S(1'b1), .Q(Q[1]));
FDCE_1 fd3(.C(C), .CE(1'b1), .D(D), .CLR(1'b1), .Q(Q[2]));
FDPE_1 fd4(.C(C), .CE(1'b1), .D(D), .PRE(1'b1), .Q(Q[3]));
endmodule
EOT
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-none t:FD*
design -reset
read_verilog <<EOT
module top(input C, D, output [3:0] Q);
FDRE_1 fd1(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[0]));
FDSE_1 fd2(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[1]));
FDCE_1 fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2]));
FDPE_1 fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3]));
endmodule
EOT
equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf
design -load postopt
select -assert-none t:FD*