mirror of https://github.com/YosysHQ/yosys.git
Custom step to add global clock buffers
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6e210f26fa
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@ -1,5 +1,6 @@
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OBJS += techlibs/efinix/synth_efinix.o
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OBJS += techlibs/efinix/efinix_gbuf.o
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$(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v))
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$(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v))
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@ -34,3 +34,11 @@ module EFX_FF(
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parameter SR_SYNC_PRIORITY = 0;
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parameter D_POLARITY = 1;
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endmodule
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module EFX_GBUFCE (
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input CE,
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input I,
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output O
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);
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parameter CE_POLARITY = 1'b1;
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endmodule
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@ -0,0 +1,113 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2019 Miodrag Milanovic <miodrag@symbioticeda.com>
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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static void handle_gbufs(Module *module)
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{
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SigMap sigmap(module);
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pool<SigBit> clk_bits;
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dict<SigBit, SigBit> rewrite_bits;
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vector<pair<Cell*, SigBit>> pad_bits;
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for (auto cell : module->cells())
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{
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if (cell->type == "\\EFX_FF") {
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for (auto bit : sigmap(cell->getPort("\\CLK")))
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clk_bits.insert(bit);
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}
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}
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for (auto wire : vector<Wire*>(module->wires()))
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{
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if (!wire->port_input)
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continue;
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for (int index = 0; index < GetSize(wire); index++)
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{
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SigBit bit(wire, index);
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SigBit canonical_bit = sigmap(bit);
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if (!clk_bits.count(canonical_bit))
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continue;
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Cell *c = module->addCell(NEW_ID, "\\EFX_GBUFCE");
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SigBit new_bit = module->addWire(NEW_ID);
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c->setParam("\\CE_POLARITY", State::S1);
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c->setPort("\\O", new_bit);
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c->setPort("\\CE", State::S1);
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pad_bits.push_back(make_pair(c, bit));
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rewrite_bits[canonical_bit] = new_bit;
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log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
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}
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}
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auto rewrite_function = [&](SigSpec &s) {
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for (auto &bit : s) {
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SigBit canonical_bit = sigmap(bit);
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if (rewrite_bits.count(canonical_bit))
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bit = rewrite_bits.at(canonical_bit);
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}
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};
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module->rewrite_sigspecs(rewrite_function);
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for (auto &it : pad_bits)
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it.first->setPort("\\I", it.second);
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}
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struct EfinixGbufPass : public Pass {
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EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" efinix_gbuf [options] [selection]\n");
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log("\n");
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log("Add Efinix global clock buffers to top module as needed.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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Module *module = design->top_module();
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if (module == nullptr)
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log_cmd_error("No top module found.\n");
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handle_gbufs(module);
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}
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} EfinixGbufPass;
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PRIVATE_NAMESPACE_END
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@ -181,6 +181,12 @@ struct SynthEfinixPass : public ScriptPass
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run("clean");
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}
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if (check_label("map_gbuf"))
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{
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run("efinix_gbuf");
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run("clean");
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}
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if (check_label("check"))
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{
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run("hierarchy -check");
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