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Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position 

write_verilog: fix placement of case attributes
This commit is contained in:
Clifford Wolf 2019-07-09 22:51:25 +02:00 committed by GitHub
parent f604aa174e 37bb6b5e96
commit 6dd33be7ce
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 3 deletions
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5
backends/verilog/verilog_backend.cc
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@ -1501,6 +1501,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
bool got_default = false;
for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true);
if ((*it)->compare.size() == 0) {
if (got_default)
continue;
@ -1514,9 +1515,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
dump_sigspec(f, (*it)->compare[i]);
}
}
f << stringf(":");
dump_attributes(f, indent, (*it)->attributes, ' ', /*modattr=*/false, /*as_comment=*/true);
f << stringf("\n");
f << stringf(":\n");
dump_case_body(f, indent + " ", *it);
}