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Fix handling of "logic" variables with initial value 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-06-19 11:25:11 +02:00
parent b3441935b1
commit 6d64e242ba
1 changed files with 2 additions and 2 deletions
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4
frontends/verilog/verilog_parser.y
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@ -345,7 +345,7 @@ module_arg_opt_assignment:
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
AstNode *wire = new AstNode(AST_IDENTIFIER); AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str; wire->str = ast_stack.back()->children.back()->str;
if (ast_stack.back()->children.back()->is_reg) if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
else else
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
@ -1360,7 +1360,7 @@ wire_name_and_opt_assign:
wire_name '=' expr { wire_name '=' expr {
AstNode *wire = new AstNode(AST_IDENTIFIER); AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str; wire->str = ast_stack.back()->children.back()->str;
if (astbuf1->is_reg) if (astbuf1->is_reg || astbuf1->is_logic)
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3)))); ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $3))));
else else
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));