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kernel/mem: Recognize some deprecated memory port configs. 

Transparency is meaningless for asynchronous ports, so we assume
transparent == false to simplify the code in this case.  Likewise,
enable is meaningless, and we assume it is const-1.  However,
turns out that nMigen emits the former, and Verilog frontend emits
the latter, so squash these issues when ingesting a $memrd cell.

Fixes #2811.
This commit is contained in:
Marcelina Kościelnicka 2021-06-01 01:48:35 +02:00
parent 13b901bf1c
commit 6d5d845788
1 changed files with 10 additions and 0 deletions
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10
kernel/mem.cc
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@ -291,6 +291,7 @@ void Mem::check() {
log_assert(GetSize(port.srst_value) == (width << port.wide_log2)); log_assert(GetSize(port.srst_value) == (width << port.wide_log2));
if (!port.clk_enable) { if (!port.clk_enable) {
log_assert(!port.transparent); log_assert(!port.transparent);
log_assert(port.en == State::S1);
log_assert(port.arst == State::S0); log_assert(port.arst == State::S0);
log_assert(port.srst == State::S0); log_assert(port.srst == State::S0);
} }
@ -370,6 +371,15 @@ namespace {
mrd.init_value = Const(State::Sx, mem->width << mrd.wide_log2); mrd.init_value = Const(State::Sx, mem->width << mrd.wide_log2);
mrd.srst = State::S0; mrd.srst = State::S0;
mrd.arst = State::S0; mrd.arst = State::S0;
if (!mrd.clk_enable) {
// Fix some patterns that we'll allow for backwards compatibility,
// but don't want to see moving forwards: async transparent
// ports (inherently meaningless) and async ports without
// const 1 tied to EN bit (which may mean a latch in the future).
mrd.transparent = false;
if (mrd.en == State::Sx)
mrd.en = State::S1;
}
res.rd_ports.push_back(mrd); res.rd_ports.push_back(mrd);
} }
} }